Generate VHDL ® and Verilog ® code for FPGA and ASIC designs using HDL Coder™.
This interactive, two-day course provides a guided workflow to generate and optimize your HDL code. Attend a course today and learn to generate and verify HDL code from a Simulink model using HDL...
Generate target-independent synthesizable VHDL or Verilog code directly from single-precision floating-point models.
This session demonstrates how recent developments in MATLAB ® and Simulink ® reduce the cost of developing FPGA and ASIC applications, through strong integration with...
Shorten product development time and improve quality. View a demonstration about using a MATLAB® hardware/software codesign workflow targeting Altera SoCs. The presentation was given at...
Stream heterogeneous Simulink® signals to the Logic Analyzer to perform advanced analysis and debugging.
Allegro Microsystems explains how they are leveraging MATLAB and Simulink for rapid prototyping, streamlined UVM-based verification, and automatic RTL code generation for mixed signal sensor ICs.
This presentation, made by Nokia, focuses on the usage and benefits of Simulink HDL tools targeted for rapid prototyping and verification of SoCs.
John Russell describes some of the challenges in safety-critical avionics development and how they are being overcome using Model-Based Design.
This presentation details the distance calculation algorithm for time-of-flight (ToF) 3D cameras.
This presentation focuses on how designers can use Simulink® to extend Model-Based Design to describe the functional intent using a higher abstraction level.
This presentation discusses FLIR’s experiences with using HDL Coder as a part of a streamlined project model. It also shows some of the results regarding code efficiency, reusability, and modularity.
In this presentation Ericsson shares their experiences incorporating HDL Coder into the design workflow of a new test-bed radio.
Near field communication (NFC) technology is attracting a lot of interest for mobile payment and ticketing applications. Behind the simple “swipe and go” operation is a complex system spanning many...
Discover how Punch developed an evolutionary SR motor control algorithm by using Model-Based Design with MATLAB® and Simulink® for a platform based on Zynq® -7000 SoC.
This master class shows how you can use recent developments in the MATLAB product family to develop efficient simulations and provides a flow from MATLAB code to embeddable C/C++ and HDL code...
FPGA is a technology for automotive control applications to implement peripheral and algorithmic components requiring fast turn-around time. In this session, learn techniques to model HDL components...
As computer vision algorithms become more complex, the transition from algorithm development to real-time implementation becomes critical. This presentation explores how to facilitate this...
Learn the considerations, workflow, and techniques for targeting a vision processing algorithm to FPGA hardware
Use the strengths of MATLAB® and Simulink® to deploy an algorithm to hardware.
Learn about the hardware implementation techniques used in the Vision HDL Toolbox lane detection example.
Use the HDL Coder™ State Control block to tag a subsystem and the hierarchy below it for implementation in hardware.
Sample input data in parallel to achieve gigasample per second (GSPS) signal processing using DSP System Toolbox™ FFT and IFFT HDL Optimized blocks and HDL Coder™.
Use For Each subsystems in HDL Coder to generate concise HDL code for repeated instantiations of an algorithm.
Clock rate pipelining, introduced in HDL Coder™ R2014b, inserts new pipeline stages that are clocked at the faster FPGA clock rate. This is part one of a two-part series on this feature,...
This is part two of a two-part series on this feature, showing how to use clock rate pipelining with other HDL Coder optimizations to trade off speed versus resource usage.
Generate optimized fixed-point HDL to target the lane detection example to FPGA fabric.
Use HDL Coder™ to map tunable parameters onto an AXI4, AXI4-Lite, or external interface in the generated IP core for Xilinx® Zynq® or Altera® SoC hardware.