HDL Coder

All Releases

R2015a (Version 3.6) - 5 Mar 2015

Version 3.6, part of Release 2015a, includes the following enhancements:

  • Mac OS X platform support
  • Critical path estimation without running synthesis
  • AXI4-Stream interface generation for Xilinx Zynq IP core
  • Custom reference design and custom SoC board support
  • Localized control using pragmas for pipelining, loop streaming, and loop unrolling in MATLAB code
  • Support for image processing, video, and computer vision designs in new Vision HDL Toolbox product

See the Release Notes for details.

R2014b (Version 3.5) - 2 Oct 2014

Version 3.5, part of Release 2014b, includes the following enhancements:

  • Clock-rate pipelining to optimize timing in multi-cycle paths
  • Support for Xilinx Vivado
  • IP core generation for Altera SoC platform
  • Custom or legacy HDL code integration in the MATLAB to HDL workflow

See the Release Notes for details.

R2014a (Version 3.4) - 6 Mar 2014

Version 3.4, part of Release 2014a, includes the following enhancements:

  • Code generation for enumeration data types
  • ZC706 target for IP core generation and integration into Xilinx EDK project
  • Automatic iterative clock frequency optimization
  • Code generation for FFT HDL Optimized and IFFT HDL Optimized blocks
  • HDL block library in Simulink

See the Release Notes for details.

R2013b (Version 3.3) - 5 Sep 2013

Version 3.3, part of Release 2013b, includes the following enhancements:

  • Model reference support and incremental code generation
  • Code generation for user-defined System objects
  • RAM inference in conditional MATLAB code
  • Code generation for subsystems containing Altera DSP Builder blocks
  • IP core integration into Xilinx EDK project for ZC702 and ZedBoard

See the Release Notes for details.

R2013a (Version 3.2) - 7 Mar 2013

Version 3.2, part of Release 2013a, includes the following enhancements:

  • Static range analysis for floating-point to fixed-point conversion
  • User-specified pipeline insertion for MATLAB variables
  • Resource sharing and streaming without over clocking
  • Generation of custom IP core with AXI4 interface

See the Release Notes for details.