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HDL Coder

Synchronous Subsystem Toggle

Synchronous Subsystem Toggle

Specify enable and reset behavior for cleaner HDL code by using State Control block

Watch video 01:53

Gigasample per Second (GSPS) Signal Processing

Gigasample per Second (GSPS) Signal Processing

Increase throughput of HDL-optimized FFT and IFFT algorithms using frame input

Watch video 3:17

Hard Floating-Point IP Targeting

Hard Floating-Point IP Targeting

Generate HDL to map to Altera Arria 10 floating-point units at user-specified target frequency

Resource Sharing Enhancements

Resource Sharing Enhancements

Share multipliers and gain operations that have different data types

Faster Test Bench Generation and HDL Simulation

Faster Test Bench Generation and HDL Simulation

Generate SystemVerilog DPI test benches for large data sets with HDL Verifier

Latest Releases

R2016a (Version 3.8) - 3 Mar 2016

Version 3.8, part of Release 2016a, includes the following enhancements:

  • Synchronous Subsystem Toggle: Specify enable and reset behavior for cleaner HDL code by using State Control block
  • Gigasample per Second (GSPS) Signal Processing: Increase throughput of HDL-optimized FFT and IFFT algorithms using frame input
  • Hard Floating-Point IP Targeting: Generate HDL to map to Altera Arria 10 floating-point units at user-specified target frequency
  • Resource Sharing Enhancements: Share multipliers and gain operations that have different data types
  • Faster Test Bench Generation and HDL Simulation: Generate SystemVerilog DPI test benches for large data sets with HDL Verifier

See the Release Notes for details.

R2015aSP1 (Version 3.6.1) - 14 Oct 2015

Version 3.6.1, part of Release 2015aSP1, includes bug fixes.

See the Release Notes for details.

R2015b (Version 3.7) - 3 Sep 2015

Version 3.7, part of Release 2015b, includes the following enhancements:

  • Tunable Parameters: Map Tunable Parameters to AXI4 Interface with HDL Coder 2:08
  • Expanded Bus Support: Generate HDL for enabled or triggered subsystems with bus inputs and for black boxes with bus I/O
  • Quality of Results Improvement: Stream and share resources more broadly and efficiently
  • Model Arguments: Parameterize instances of model reference blocks
  • End-to-end scripting from design through IP core generation, FPGA Turnkey, and generic ASIC/FPGA workflows

See the Release Notes for details.

R2015a (Version 3.6) - 5 Mar 2015

Version 3.6, part of Release 2015a, includes the following enhancements:

  • Mac OS X platform support
  • Critical path estimation without running synthesis
  • AXI4-Stream interface generation for Xilinx Zynq IP core
  • Custom reference design and custom SoC board support
  • Localized control using pragmas for pipelining, loop streaming, and loop unrolling in MATLAB code
  • Support for image processing, video, and computer vision designs in new Vision HDL Toolbox product

See the Release Notes for details.

R2014b (Version 3.5) - 2 Oct 2014

Version 3.5, part of Release 2014b, includes the following enhancements:

  • Clock-rate pipelining to optimize timing in multi-cycle paths
  • Support for Xilinx Vivado
  • IP core generation for Altera SoC platform
  • Custom or legacy HDL code integration in the MATLAB to HDL workflow

See the Release Notes for details.

R2014a (Version 3.4) - 6 Mar 2014

Version 3.4, part of Release 2014a, includes the following enhancements:

  • Code generation for enumeration data types
  • ZC706 target for IP core generation and integration into Xilinx EDK project
  • Automatic iterative clock frequency optimization
  • Code generation for FFT HDL Optimized and IFFT HDL Optimized blocks
  • HDL block library in Simulink

See the Release Notes for details.