HDL Verifier

What's New

R2015a (Version 4.6) - Released 5 Mar 2015

Version 4.6, part of Release 2015a, includes the following enhancements:

  • FPGA-in-the-loop through JTAG for Xilinx boards
  • FPGA-in-the-Loop support for rapid accelerator mode in Simulink
  • DPI-C enhancements, including multiple-instance support and integration with build toolchain
  • IP-XACT support for TLM

See the Release Notes for details.

Previous Releases

R2014b (Version 4.5) - 2 Oct 2014

Version 4.5, part of Release 2014b, includes the following enhancements:

  • SystemVerilog DPI-C component generation based on MATLAB Coder
  • SystemVerilog DPI-C component generation based on Simulink Coder
  • Xilinx Vivado support for FPGA-in-the-Loop

See the Release Notes for details.

R2014a (Version 4.4) - 6 Mar 2014

Version 4.4, part of Release 2014a, includes the following enhancements:

  • FPGA-in-the-Loop over JTAG for Altera FPGAs
  • Parameter Tuning for Generated TLM Component
  • Multiple Socket Control for Generated TLM Component
  • FPGA-in-the-Loop support for Altera Cyclone V SoC FPGA boards

See the Release Notes for details.

R2013b (Version 4.3) - 5 Sep 2013

Version 4.3, part of Release 2013b, includes the following enhancements:

  • SystemVerilog DPI component generation from Simulink
  • BEEcube miniBEE FPGA-in-the-Loop (FIL) support package
  • Additional FPGA board support for FIL, including Xilinx KC705 and Altera DSP Development Kit, Stratix V edition
  • Floating-point data type for cosimulation and FIL blocks
  • HDL file compilation ordering in Cosimulation Wizard

See the Release Notes for details.

R2013a (Version 4.2) - 7 Mar 2013

Version 4.2, part of Release 2013a, includes the following enhancements:

  • FPGA-in-the-loop testbench generation through HDL Workflow Advisor for MATLAB
  • HDL cosimulation testbench generation through HDL Workflow Advisor for MATLAB
  • Transaction Level Model generation using Simulink Coder

See the Release Notes for details.