Simulink Design Verifier
Identify and isolate design errors and generate tests
Simulink Design Verifier™ uses formal methods to identify hidden design errors in models without extensive simulation runs. It detects blocks in the model that result in integer overflow, dead logic, array access violations, division by zero, and requirement violations. For each error it produces a simulation test case for debugging.
Simulink Design Verifier generates test inputs for model coverage and custom objectives. It also lets you augment and extend existing test cases. These test cases drive your model to satisfy condition, decision, modified condition/decision (MCDC), and custom coverage objectives.
The Model Slicer tool in Simulink Design Verifier isolates problematic behavior in a model using a combination of dynamic and static analysis. It lets you highlight and trace functional dependencies of ports, signals, and blocks, and slice a large model into smaller, standalone models for analysis. You can view blocks affecting a subsystem output and trace a signal path through multiple switches and logic. The Variant Reducer tool enables you to simplify models containing multiple variants by creating sliced models based on active variant configurations.
From Paul Urban, Simulink Design Verifier Technical Expert