For FPGA and ASIC designs, you can use HDL Coder™ and HDL Verifier™ to specify and explore functional behavior, generate HDL code for implementation, and continuously test and verify your design through cosimulation with HDL simulators or FPGA-in-the-loop.
You can generate synthesizable HDL code for FPGA and ASIC implementations in a few steps:
Using HDL Coder, you can automatically convert MATLAB code from floating point to fixed point and generate synthesizable VHDL and Verilog code. With this capability, you can model your algorithm at a high level using MATLAB constructs and System objects while utilizing options for optimizing generated HDL code. You can use the library of ready-to-use logic elements, such as counters and timers, which are written in MATLAB.
You can use HDL Coder to generate VHDL and Verilog code from Simulink and Stateflow®. With Simulink, you can model your algorithm using a library of more than 200 blocks. This library provides complex functions, such as the Viterbi decoder, FFT, CIC filters, and FIR filters, for modeling signal processing and communications systems and generating HDL code. You can use HDL Coder for IP core generation targeting Altera and Xilinx FPGAs and SoC FPGAs.
Using HDL Coder, you can program FPGAs, including devices from Altera®, Xilinx®, and other FPGA vendors. This capability helps you quickly prototype your design on FPGA hardware. The Workflow Advisor in HDL Coder integrates with Xilinx ISE® and Altera Quartus® II design suites to automatically program your FPGAs from within MATLAB and Simulink.
You can use HDL Coder to prototype your algorithm on a variety of Xilinx and Altera FPGA development boards. Additionally, you can use target-independent HDL code to program FPGA devices from vendors like Microsemi® or Lattice Semiconductor®.
You can reuse your MATLAB and Simulink testbench to verify your HDL code using cosimulation and FPGA-in-the-loop functionality provided by HDL Verifier.
When used with HDL Verifier, HDL Coder automatically generates cosimulation and FPGA-in-the-loop models to accelerate the workflow for FPGA or ASIC design verification. This approach eliminates the need to manually transfer test vectors and helps identify errors earlier in the ASIC design process.