Accelerating the pace of engineering and science

Accelerate FPGA Design Using Simulink HDL Coder

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Stephan Van Beek, MathWorks

In this webinar you will learn how you can leverage Simulink HDL Coder to accelerate your FPGA design cycle and avoid costly mistakes. Using Simulink and Simulink HDL Coder you can do rapid prototyping on FPGAs or implement your design on ASICs and FPGAs.

MathWorks engineers will demonstrate the latest enhancements to Simulink HDL Coder, which generates synthesizable Verilog® and VHDL® code from Simulink models, MATLAB code, and Stateflow charts.

Topics include:

  • Simulink system level design
  • Automatic HDL code generation using Simulink HDL Coder
  • Optimization techniques for efficient FPGA implementation
  • HDL Workflow Advisor
  • Code Traceability for safety critical applications like DO-254

About the Presenter: Stephan van Beek is a Signal Processing and Communications Engineer Application Engineer for MathWorks focused on FPGA implementation. Prior to joining MathWorks, Stephan worked at Océ-Netherlands as an application engineer responsible for FPGA tool flows. He has also worked as a field service engineer for motion control systems at Anorad Europe BV. Stephan studied electrical engineering at the Polytechnic in Eindhoven.

Product Focus

  • HDL Coder
  • HDL Verifier
  • Filter Design HDL Coder

Recorded: 19 Oct 2010