Accelerating the pace of engineering and science

Connecting Simulink with your SystemVerilog Workflow for Functional Verification

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Sudeepa Prakash, MathWorks

Learn how you can increase the productivity of your FPGA and ASIC verification process by exporting MATLAB and Simulink models into your SystemVerilog environment at this webinar.

Using HDL Verifier, with Embedded Coder, you can export a Simulink subsystem as a SystemVerilog component, with a Direct Programming Interface (DPI) for behavioral simulation. You can model and export algorithms, components, environment models and data sources using this technology.

With this workflow you can:

  1. Generate C code from your Simulink model
  2. Automatically wrap the C code using the DPI-C interface
  3. Import, build and simulate an equivalent behavioral SystemVerilog model in your IC design tool

About the Presenter

Sudeepa Prakash is product marketing manager for HDL code generation and verification products at MathWorks. Prior to joining MathWorks, she was an embedded software engineer at Johnson Controls Inc. Sudeepa has also worked with scientists at LRDE in India on digital modules for radar systems using HDL code generation. She has a master’s degree in computer science from the University of Wisconsin- Milwaukee and a bachelor’s in electronics and communications from Visvesvaraya Technological University

Product Focus

  • HDL Verifier

Recorded: 19 Aug 2014