From the series: Design and Verify Signal Processing and Communications Systems
Giovanni Mancini, MathWorks
As you develop complex signal processing algorithms and systems, how do you verify that your design works as intended in context with the entire system? Do you find that you are spending more time on testing than on developing algorithm IP for your products?
This webinar is the first of a three-part series that demonstrates techniques for reducing verification time by eliminating design flaws earlier in your development process. This webinar focuses on modeling and simulation, and upcoming webinars will describe techniques for accelerating verification of HDL and embedded C code.
This webinar will describe approaches for modeling systems with complex timing, control logic, and analog and digital system components. As an example, it will provide an in-depth demonstration of a digital pre-distortion DSP techniques to compensate for nonlinear RF components in a wireless base station. The demonstration will cover:
• Fixed-point DSP algorithm development
• RF behavioral modeling
• Test Bench creation
• BER simulation and analysis
No prior knowledge of MATLAB or Simulink is required for this webinar.
Recorded: 25 March 2009
Part 1 Modeling and Simulation As you develop complex signal processing algorithms and systems, how do you verify that your design works as intended in context with the entire system?
Part 2 HDL Functional Verification In this webinar we will explore how the EDA Simulator Links allow MATLAB or Simulink and your HDL Simulator to work together to create a better debug and verification environment to improve your product quality and shorten your development time. Thro
Part 3 DSP Early Software Verification This webinar is the third of a three-part series that demonstrates how you can reduce verification time by eliminating design flaws earlier in your development process. In this webinar we will introduce the following MathWorks DSP verification produc