Design and Verify Signal Processing and Communications Systems, Part 2: HDL Functional Verification

From the series: Design and Verify Signal Processing and Communications Systems

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David Lidrbauch, MathWorks

In this webinar we will explore how the EDA Simulator Links allow MATLAB or Simulink and your HDL Simulator to work together to create a better debug and verification environment to improve your product quality and shorten your development time.

Through demonstrations and explanations you will learn about how this cosimulation capability plugs into your existing design flow. You will see how this eliminates time-consuming and repetitive tasks, improves the quality of debug and verification, and increases verification throughput 4x – 10x.

In this webinar we will show how using Simulink or MATLAB with your HDL simulator simultaneously allows you to:

• Use the algorithm specification in MATLAB or Simulink to directly improve your test bench
• Join verification environments for interactive cosimulation and debug
• Perform subjective analysis in MATLAB or Simulink while using your HDL simulator
• Use automatic test bench creation to eliminate manual scripting
• Eliminate manual stimulus and response data capture
• Use automatic code generation to create better test benches
• Accelerate to prototyping hardware (using HDL Code Generation) from MATLAB or Simulink.

Product Focus

  • HDL Verifier
  • Aerospace Blockset
  • Filter Design HDL Coder
  • MATLAB
  • Simulink
  • HDL Coder

Recorded: 14 May 2009

Series: Design and Verify Signal Processing and Communications Systems

Part 1: Modeling and Simulation
As you develop complex signal processing algorithms and systems, how do you verify that your design works as intended in context with the entire system? Do you find that you are spending more time on testing than on developing algorithm IP for your p

Part 2: HDL Functional Verification
In this webinar we will explore how the EDA Simulator Links allow MATLAB or Simulink and your HDL Simulator to work together to create a better debug and verification environment to improve your product quality and shorten your development time. Thro

Part 3: DSP Early Software Verification
This webinar is the third of a three-part series that demonstrates how you can reduce verification time by eliminating design flaws earlier in your development process. In this webinar we will introduce the following MathWorks DSP verification produc