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| R2012a Documentation → Communications System Toolbox | |
Learn more about Communications System Toolbox |
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CRC sublibrary of Error Correction and Detection
The General CRC Generator block generates cyclic redundancy code (CRC) bits for each input data frame and appends them to the frame. This block accepts a binary column vector input signal.
You specify the generator polynomial for the CRC algorithm using the Generator polynomial parameter. This block is general in the sense that the degree of the polynomial does not need to be a power of two. You represent the polynomial in one of these ways:
As a binary row vector containing the coefficients in descending order of powers. For example, [1 1 0 1] represents the polynomial x3 + x2 + 1.
As an integer row vector containing the powers of nonzero terms in the polynomial, in descending order. For example, [3 2 0] represents the polynomial x3 + x2 + 1.
You specify the initial state of the internal shift register by the Initial states parameter. The Initial states parameter is either a scalar or a binary row vector of length equal to the degree of the generator polynomial. A scalar value is expanded to a row vector of length equal to the degree of the generator polynomial. For example, the default initial state of [0] is expanded to a row vector of all zeros.
You specify the number of checksums that the block calculates for each input frame by the Checksums per frame parameter. The Checksums per frame value must evenly divide the size of the input frame. If the value of Checksums per frame is k, the block does the following:
Divides each input frame into k subframes of equal size
Prefixes the Initial states vector to each of the k subframes
Applies the CRC algorithm to each augmented subframe
Appends the resulting checksums at the end of each subframe
Outputs concatenated subframes
If the size of the input frame is m and the degree of the generator polynomial is r, the output frame has size m + k * r.
This block supports double and boolean data types. The block inherits the output data type from the input signal.
Suppose the size of the input frame is 10, the degree of the generator polynomial is 3, Initial states is [0], and Checksums per frame is 2. The block divides each input frame into two subframes of size 5 and appends a checksum of size 3 to each subframe, as shown below. The initial states are not shown in this example, because an initial state of [0] does not affect the output of the CRC algorithm. The output frame then has size 5 + 3 + 5 + 3 = 16.
This example clarifies the operation of the General CRC Generator block by comparing the generated CRC bits from the library block with those generated from primitive Simulink blocks. The model is located at: matlabroot/help/toolbox/commblks/examples/doc_crcgen.
For a known input message with a length of 6 bits, the model
generates CRC bits for a generator polynomial,
, and a specific initial state
of the register.
You can experiment with different initial states by changing the value of Initial states prior to running the simulation. For all values, the comparison (generated CRC bits from the library block with those generated from primitive Simulink blocks) holds true.
Using the General CRC Generator block allows you to easily specify the generator polynomial (especially for higher order polynomials).
The General CRC Generator block has one input port and one output port. Both ports support binary column vector signals.
A binary or integer row vector specifying the generator polynomial, in descending order of powers.
Binary scalar or a binary row vector of length equal to the degree of the generator polynomial, specifying the initial state of the internal shift register.
Positive integer specifying the number of checksums the block calculates for each input frame.
For a description of the CRC algorithm as implemented by this block, see Cyclic Redundancy Check Codes in Communications System Toolbox User's Guide.
The previous circuit divides the polynomial
by
, and returns the remainder
.
The circuits feeds the input symbols
into the shift register one
at a time, in order of decreasing index. When the last symbol (
) works its way out of the register
(achieved by augmenting the message with r zeros),
the register contains the coefficients of the remainder polynomial
.
This remainder polynomial is the checksum that is appended to the original message, which is then transmitted.
While functionally correct, this circuit is slow because it handles the input symbols one at a time, and uses one XOR operation for each input symbol. A more efficient implementation would handle N input symbols in each processing step. For example, when computing a CRC of length K, where K < 8, process N = K bits in each step. If K ≥ 8, process N = 8 bits in each step.
For this faster algorithm, you can use a look-ahead table that stores the effect each possible length-N input sequence has on the CRC output value. This implementation uses only one XOR operation to process a length-N subsequence of the augmented input symbol stream. If there are leftover bits at the end of the stream that cannot be formed into a length-N sequence, this implementation handles the bits individually, using the slow algorithm previously described.
[1] Sklar, Bernard, Digital Communications: Fundamentals and Applications. Englewood Cliffs, N.J., Prentice-Hall, 1988.
[2] Wicker, Stephen B., Error Control Systems for Digital Communication and Storage, Upper Saddle River, N.J., Prentice Hall, 1995.
CRC-N Generator, CRC-N Syndrome Detector
Learn how to apply early verification to your development process through these technical resources.
How much time do you spend on testing to ensure implementation meets system-level requirements?
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