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Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL

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Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL

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17 Sep 2007 (Updated )

Model-Based Design of a Sigma-Delta ADC, from behavioral model to VHDL code.

y=bin2sbin(x)
function y=bin2sbin(x)

    y = ones(1,length(x));

    for index =1:length(x)
    
        if x(index)=='0'
            y(index)=-1;
        end
        
    end
    

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