%---------------------------------------------------
% Ce programme est la propriete exclusive de SUPELEC
% Tout usage non authorise ou reproduction de ce
% programme est strictement defendu.
% Copyright (c) 2010 SUPELEC Departement SSE
% Tous droits reserves
%---------------------------------------------------
%
% fichier : create_vhdl_model_cdn.m
% auteur : P.BENABES & C.TUGUI
% Copyright (c) 2010 SUPELEC
% Revision: 2.0 Date: 29/10/2010
%
%---------------------------------------------------
%
% DESCRIPTION DU MODULE :
%
%
% MODULES UTILISES :
%
%---------------------------------------------------
function filepath_vhd=create_verilog_model(vhdl_model_par,model_in_out,multi_in_out,filepath_vhd)
% Create vhdl model starting from extracted characteristics
% Open or create the vhd and the pat file:
if isempty(filepath_vhd)
filename = strcat('VERILOG/Models/', vhdl_model_par.subcell, '_cdn.va');
[file,path] = uiputfile('*.va', 'Extract VHDL-AMS Model -> write CADENCE .va', filename);
if (file(1)~=0)&&(path(1)~=0)
filepath_vhd=[path file];
fid = fopen(filepath_vhd, 'w');
else
return
end
else
fid = fopen(filepath_vhd, 'w');
end
%Number of outputs
no=vhdl_model_par.numout;
%Create model .vhd file
% Write the first lines:
fprintf(fid, '%s\n', '//-------------------------------------');
fprintf(fid, '%s\n', '// Generated by SIMECT');
fprintf(fid, '%s', '// Generated on: ');
fprintf(fid, '%s\n', datestr(now));
fprintf(fid, '%s\n', '//-------------------------------------');
fprintf(fid, '%s\n', '');
fprintf(fid, '%s\n', '`include "constants.vams"');
fprintf(fid, '%s\n', '`include "disciplines.vams"');
fprintf(fid, '%s\n', '');
fprintf(fid, 'module %s (', vhdl_model_par.subcell);
if vhdl_model_par.gen_sources
if vhdl_model_par.gen_supply
fprintf(fid, '%s',[strrep(vhdl_model_par.alim_Vname,'net_','') ',']);
end
end
if ~isempty(vhdl_model_par.gnd)
fprintf(fid, '%s',[strrep(vhdl_model_par.gnd,'net_','') ',']);
end
for i=1:size(vhdl_model_par.in_Vname,2)
fprintf(fid, '%s',[strrep(vhdl_model_par.in_Vname{i},'net_','') ',']);
end
for i=1:size(vhdl_model_par.out_Vname,2)-1
fprintf(fid, '%s',[strrep(vhdl_model_par.out_Vname{i},'net_','') ',']);
end
fprintf(fid, '%s\n', [strrep(vhdl_model_par.out_Vname{size(vhdl_model_par.out_Vname,2)},'net_','') ');']);
if vhdl_model_par.gen_sources
if vhdl_model_par.gen_supply
fprintf(fid, 'input %s;\n',strrep(vhdl_model_par.alim_Vname,'net_','') );
fprintf(fid, 'electrical %s;\n',strrep(vhdl_model_par.alim_Vname,'net_','') );
end
end
if ~isempty(vhdl_model_par.gnd)
fprintf(fid, 'input %s;\n',strrep(vhdl_model_par.gnd,'net_','') );
fprintf(fid, 'electrical %s;\n',strrep(vhdl_model_par.gnd,'net_','') );
end
for i=1:size(vhdl_model_par.in_Vname,2)
fprintf(fid, 'input %s;\n',strrep(vhdl_model_par.in_Vname{i},'net_','') );
fprintf(fid, 'electrical %s;\n',strrep(vhdl_model_par.in_Vname{i},'net_','') );
end
for i=1:size(vhdl_model_par.out_Vname,2)
fprintf(fid, 'output %s;\n',strrep(vhdl_model_par.out_Vname{i},'net_','') );
fprintf(fid, 'electrical %s;\n',strrep(vhdl_model_par.out_Vname{i},'net_','') );
end
fprintf(fid, '%s\n', '');
% Copy the parameters:
for i=1:no
% TFD1
model_in_out{i}.TF_dir1=decomp_write_tf_verilog(1,fid,i,'TF_dir1',model_in_out{i}.Num_TF_dir1,model_in_out{i}.Den_TF_dir1,0);
if vhdl_model_par.mode_diff_enabled_out
% TFD2
model_in_out{i}.TF_dir2=decomp_write_tf_verilog(1,fid,i,'TF_dir2',model_in_out{i}.Num_TF_dir2,model_in_out{i}.Den_TF_dir2,0);
end
if vhdl_model_par.mode_diff_enabled
% TFD3
model_in_out{i}.TF_dir3=decomp_write_tf_verilog(1,fid,i,'TF_dir3',model_in_out{i}.Num_TF_dir3,model_in_out{i}.Den_TF_dir3,0);
if vhdl_model_par.mode_diff_enabled_out
% TFD4
model_in_out{i}.TF_dir4=decomp_write_tf_verilog(1,fid,i,'TF_dir4',model_in_out{i}.Num_TF_dir4,model_in_out{i}.Den_TF_dir4,0);
end
end
if vhdl_model_par.rev_trfunction
% TFR1
model_in_out{i}.TF_inv1=decomp_write_tf_verilog(1,fid,i,'TF_inv1',model_in_out{i}.Num_TF_inv1,model_in_out{i}.Den_TF_inv1,0);
if vhdl_model_par.mode_diff_enabled_out
% TFR2
model_in_out{i}.TF_inv2=decomp_write_tf_verilog(1,fid,i,'TF_inv2',model_in_out{i}.Num_TF_inv2,model_in_out{i}.Den_TF_inv2,0);
end
if vhdl_model_par.mode_diff_enabled
% TFR3
model_in_out{i}.TF_inv3=decomp_write_tf_verilog(1,fid,i,'TF_inv3',model_in_out{i}.Num_TF_inv3,model_in_out{i}.Den_TF_inv3,0);
if vhdl_model_par.mode_diff_enabled_out
% TFR4
model_in_out{i}.TF_inv4=decomp_write_tf_verilog(1,fid,i,'TF_inv4',model_in_out{i}.Num_TF_inv4,model_in_out{i}.Den_TF_inv4,0);
end
end
end
% Zin1
model_in_out{i}.Zin1=decomp_write_tf_verilog(1,fid,i,'Zin1',model_in_out{i}.Num_Zin1,model_in_out{i}.Den_Zin1,vhdl_model_par.model_name(1)=='V');
if vhdl_model_par.mode_diff_enabled
% Zin2
model_in_out{i}.Zin2=decomp_write_tf_verilog(1,fid,i,'Zin2',model_in_out{i}.Num_Zin2,model_in_out{i}.Den_Zin2,vhdl_model_par.model_name(1)=='V');
% Zin_diff1
model_in_out{i}.Zin_diff1=decomp_write_tf_verilog(1,fid,i,'Zin_diff1',model_in_out{i}.Num_Zin_diff1,model_in_out{i}.Den_Zin_diff1,vhdl_model_par.model_name(1)=='V');
% Zin_diff2
model_in_out{i}.Zin_diff2=decomp_write_tf_verilog(1,fid,i,'Zin_diff2',model_in_out{i}.Num_Zin_diff2,model_in_out{i}.Den_Zin_diff2,vhdl_model_par.model_name(1)=='V');
end
% Zout1
model_in_out{i}.Zout1=decomp_write_tf_verilog(1,fid,i,'Zout1',model_in_out{i}.Num_Zout1,model_in_out{i}.Den_Zout1,vhdl_model_par.model_name(3)=='C');
if vhdl_model_par.mode_diff_enabled_out
% Zout2
model_in_out{i}.Zout2=decomp_write_tf_verilog(1,fid,i,'Zout2',model_in_out{i}.Num_Zout2,model_in_out{i}.Den_Zout2,vhdl_model_par.model_name(3)=='C');
% Zout_diff1
%model_in_out{i}.Zout_diff1=decomp_write_tf_vhdl(1,fid,i,'Zout_diff1',model_in_out{i}.Num_Zout_diff1,model_in_out{i}.Den_Zout_diff1,0);
% Zout_diff2
%model_in_out{i}.Zout_diff2=decomp_write_tf_vhdl(1,fid,i,'Zout_diff2',model_in_out{i}.Num_Zout_diff2,model_in_out{i}.Den_Zout_diff2,0);
end
% Offsets
write_verilog_real(fid, ['Out_' num2str(i) '_' 'OffIn11'],model_in_out{i}.OffIn11);
write_verilog_real(fid, ['Out_' num2str(i) '_' 'OffIn12'],model_in_out{i}.OffIn12);
if vhdl_model_par.mode_diff_enabled
write_verilog_real(fid, ['Out_' num2str(i) '_' 'OffIn21'],model_in_out{i}.OffIn21);
write_verilog_real(fid, ['Out_' num2str(i) '_' 'OffIn22'],model_in_out{i}.OffIn22);
end
write_verilog_real(fid, ['Out_' num2str(i) '_' 'OffOut11'],model_in_out{i}.OffOut11);
write_verilog_real(fid, ['Out_' num2str(i) '_' 'OffOut12'],model_in_out{i}.OffOut12);
if vhdl_model_par.mode_diff_enabled_out
write_verilog_real(fid, ['Out_' num2str(i) '_' 'OffOut21'],model_in_out{i}.OffOut21);
write_verilog_real(fid, ['Out_' num2str(i) '_' 'OffOut22'],model_in_out{i}.OffOut22);
end
end
fprintf(fid, '%s\n', '');
fprintf(fid,'real Vin1 ;\n');
fprintf(fid,'real Iin1 ;\n');
if vhdl_model_par.mode_diff_enabled
fprintf(fid,'real Vin2 ;\n');
fprintf(fid,'real Iin2 ;\n');
end
for i=1:no
fprintf(fid,'real Vout1_%s ;\n',num2str(i));
fprintf(fid,'real Iout1_%s ;\n',num2str(i));
% fprintf(fid, '%s\n',[ ' QUANTITY Vout1_' num2str(i) ' ACROSS Iout1_' num2str(i) ' THROUGH ' strrep(vhdl_model_par.out_Vname{2*i-1},'net_','') ' TO ground; ']);
if vhdl_model_par.mode_diff_enabled_out
fprintf(fid,'real Vout2_%s ;\n',num2str(i));
fprintf(fid,'real Iout2_%s ;\n',num2str(i));
% fprintf(fid, '%s\n',[ ' QUANTITY Vout2_' num2str(i) ' ACROSS Iout2_' num2str(i) ' THROUGH ' strrep(vhdl_model_par.out_Vname{2*i},'net_','') ' TO ground; ']);
end
end
if vhdl_model_par.model_name(1)=='V' % V in
fprintf(fid,'real deltaVin1 ;\n');
if vhdl_model_par.mode_diff_enabled
fprintf(fid,'real deltaVin2 ;\n');
end
else
fprintf(fid,'real deltaIin1 ;\n');
if vhdl_model_par.mode_diff_enabled
fprintf(fid,'real deltaIin2 ;\n');
end
end
if vhdl_model_par.model_name(3)=='V' % V in
for i=1:no
fprintf(fid,'real deltaIout1_%s ;\n',num2str(i));
if vhdl_model_par.mode_diff_enabled_out
fprintf(fid,'real deltaIout2_%s ;\n',num2str(i));
end
end
else
for i=1:no
fprintf(fid,'real deltaVout1_%s ;\n',num2str(i));
if vhdl_model_par.mode_diff_enabled_out
fprintf(fid,'real deltaVout2_%s ;\n',num2str(i));
end
end
end
fprintf(fid, '%s\n', '');
fprintf(fid, 'analog \n');
fprintf(fid, 'begin \n');
fprintf(fid, '%s\n', '');
if vhdl_model_par.model_name(1)=='V' % V in
fprintf(fid, [ ' Vin1 = V(' strrep(vhdl_model_par.in_Vname{1},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') '); \n']);
fprintf(fid, [ ' I(' strrep(vhdl_model_par.in_Vname{1},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') ') <+ Iin1 ; \n']);
else
fprintf(fid, [ ' Iin1 = I(' strrep(vhdl_model_par.in_Vname{1},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') '); \n']);
fprintf(fid, [ ' V(' strrep(vhdl_model_par.in_Vname{1},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') ') <+ Vin1 ; \n']);
end
if vhdl_model_par.mode_diff_enabled
if vhdl_model_par.model_name(1)=='V' % V in
fprintf(fid, [ ' Vin2 = V(' strrep(vhdl_model_par.in_Vname{2},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') '); \n']);
fprintf(fid, [ ' I(' strrep(vhdl_model_par.in_Vname{2},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') ') <+ Iin2 ; \n']);
else
fprintf(fid, [ ' Iin2 = I(' strrep(vhdl_model_par.in_Vname{2},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') '); \n']);
fprintf(fid, [ ' V(' strrep(vhdl_model_par.in_Vname{2},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') ') <+ Vin2 ; \n']);
end
end
for i=1:no
if vhdl_model_par.model_name(3)=='C' % V out
fprintf(fid, [ ' Vout1_' num2str(i) ' = V(' strrep(vhdl_model_par.out_Vname{1},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') '); \n']);
fprintf(fid, [ ' I(' strrep(vhdl_model_par.out_Vname{1},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') ') <+ Iout1_' num2str(i) ' ; \n']);
else
fprintf(fid, [ ' Iout1_' num2str(i) ' = I(' strrep(vhdl_model_par.out_Vname{1},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') '); \n']);
fprintf(fid, [ ' V(' strrep(vhdl_model_par.out_Vname{1},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') ') <+ Vout1_' num2str(i) ' ; \n']);
end
if vhdl_model_par.mode_diff_enabled_out
if vhdl_model_par.model_name(3)=='C' % V out
fprintf(fid, [ ' Vout2_' num2str(i) ' = V(' strrep(vhdl_model_par.out_Vname{2},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') '); \n']);
fprintf(fid, [ ' I(' strrep(vhdl_model_par.out_Vname{2},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') ') <+ Iout2_' num2str(i) ' ; \n']);
else
fprintf(fid, [ ' Iout2_' num2str(i) ' = I(' strrep(vhdl_model_par.out_Vname{2},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') '); \n']);
fprintf(fid, [ ' V(' strrep(vhdl_model_par.out_Vname{2},'net_','') ',' strrep(vhdl_model_par.gnd,'net_','') ') <+ Vout2_' num2str(i) ' ; \n']);
end
end
end
fprintf(fid, '%s\n', '');
if vhdl_model_par.model_name(1)=='V' % V in
fprintf(fid, '%s\n', ' deltaVin1 = Vin1 - Out_1_OffIn11;');
if vhdl_model_par.mode_diff_enabled
fprintf(fid, '%s\n', ' deltaVin2 = Vin2 - Out_1_OffIn21;');
end
else
fprintf(fid, '%s\n', ' deltaIin1 = Iin1 - Out_1_OffIn11;');
if vhdl_model_par.mode_diff_enabled
fprintf(fid, '%s\n', ' deltaIin2 = Iin2 - Out_1_OffIn21;');
end
end
if vhdl_model_par.model_name(3)=='V' % V out
for i=1:no
fprintf(fid, '%s\n', [' deltaIout1_' num2str(i) ' = Iout1_' num2str(i) ' - Out_' num2str(i) '_' 'OffOut12;']);
if vhdl_model_par.mode_diff_enabled_out
fprintf(fid, '%s\n', [' deltaIout2_' num2str(i) ' = Iout2_' num2str(i) ' - Out_' num2str(i) '_' 'OffOut22;']);
end
end
else
for i=1:no
fprintf(fid, '%s\n', [' deltaVout1_' num2str(i) ' = Vout1_' num2str(i) ' - Out_' num2str(i) '_' 'OffOut12;']);
if vhdl_model_par.mode_diff_enabled_out
fprintf(fid, '%s\n', [' deltaVout2_' num2str(i) ' = Vout2_' num2str(i) ' - Out_' num2str(i) '_' 'OffOut22;']);
end
end
end
fprintf(fid, '%s\n', '');
for i=1:no
if vhdl_model_par.model_name(3)=='V' % V out
fprintf(fid, [ ' Vout1_' num2str(i) ' =']);
else
fprintf(fid, [ ' Iout1_' num2str(i) ' =']);
end
if vhdl_model_par.model_name(1)=='V' % V in
fprintf(fid, verilog_tr_decomp('deltaVin1',i,model_in_out{i},'Num_TF_dir1','Den_TF_dir1'));
else
fprintf(fid, verilog_tr_decomp('deltaIin1',i,model_in_out{i},'Num_TF_dir1','Den_TF_dir1'));
end
if vhdl_model_par.mode_diff_enabled
if vhdl_model_par.model_name(1)=='V' % V in
fprintf(fid, verilog_tr_decomp('deltaVin2',i,model_in_out{i},'Num_TF_dir3','Den_TF_dir3'));
else
fprintf(fid, verilog_tr_decomp('deltaIin2',i,model_in_out{i},'Num_TF_dir3','Den_TF_dir3'));
end
end
if vhdl_model_par.model_name(3)=='V' % V out
fprintf(fid, verilog_tr_decomp(['deltaIout1_' num2str(i)],i,model_in_out{i},'Num_Zout1','Den_Zout1'));
else
fprintf(fid, verilog_tr_decomp(['deltaVout1_' num2str(i)],i,model_in_out{i},'Den_Zout1','Num_Zout1'));
end
fprintf(fid, '%s\n',[ ' + Out_' num2str(i) '_' 'OffOut11;']);
if vhdl_model_par.mode_diff_enabled_out
if vhdl_model_par.model_name(3)=='V' % V out
fprintf(fid, [ ' Vout2_' num2str(i) ' =']);
else
fprintf(fid, [ ' Iout2_' num2str(i) ' =']);
end
if vhdl_model_par.model_name(1)=='V' % V in
fprintf(fid, verilog_tr_decomp('deltaVin1',i,model_in_out{i},'Num_TF_dir2','Den_TF_dir2'));
else
fprintf(fid, verilog_tr_decomp('deltaIin1',i,model_in_out{i},'Num_TF_dir2','Den_TF_dir2'));
end
if vhdl_model_par.mode_diff_enabled
if vhdl_model_par.model_name(1)=='V' % V in
fprintf(fid, verilog_tr_decomp('deltaVin2',i,model_in_out{i},'Num_TF_dir4','Den_TF_dir4'));
else
fprintf(fid, verilog_tr_decomp('deltaIin2',i,model_in_out{i},'Num_TF_dir4','Den_TF_dir4'));
end
end
if vhdl_model_par.model_name(3)=='V' % V out
fprintf(fid, verilog_tr_decomp(['deltaIout2_' num2str(i)],i,model_in_out{i},'Num_Zout2','Den_Zout2'));
else
fprintf(fid, verilog_tr_decomp(['deltaVout2_' num2str(i)],i,model_in_out{i},'Den_Zout2','Num_Zout2'));
end
fprintf(fid, '%s\n',[ ' + Out_' num2str(i) '_' 'OffOut21;']);
end
end
if vhdl_model_par.model_name(1)=='V' % V in
fprintf(fid, [ ' Iin1 = ' verilog_tr_decomp('deltaVin1',1,model_in_out{1},'Den_Zin1','Num_Zin1') ]);
if vhdl_model_par.mode_diff_enabled
fprintf(fid, verilog_tr_decomp('deltaVin2',1,model_in_out{1},'Den_Zin_diff2','Num_Zin_diff2'));
end
else
fprintf(fid, [ ' Vin1 = ' verilog_tr_decomp('deltaIin1',1,model_in_out{1},'Num_Zin1','Den_Zin1') ]);
if vhdl_model_par.mode_diff_enabled
fprintf(fid, verilog_tr_decomp('deltaIin2',1,model_in_out{1},'Num_Zin_diff1','Den_Zin_diff1'));
end
end
if vhdl_model_par.rev_trfunction
for i=1:no
if vhdl_model_par.model_name(3)=='V' % V out
fprintf(fid, verilog_tr_decomp(['deltaIout1_' num2str(i)],i,model_in_out{i},'Num_TF_inv1','Den_TF_inv1'));
if vhdl_model_par.mode_diff_enabled_out
fprintf(fid, verilog_tr_decomp(['deltaIout2_' num2str(i)],i,model_in_out{i},'Num_TF_inv2','Den_TF_inv2'));
end
else
fprintf(fid, verilog_tr_decomp(['deltaVout1_' num2str(i)],i,model_in_out{i},'Num_TF_inv1','Den_TF_inv1'));
if vhdl_model_par.mode_diff_enabled_out
fprintf(fid, verilog_tr_decomp(['deltaVout2_' num2str(i)],i,model_in_out{i},'Num_TF_inv2','Den_TF_inv2'));
end
end
end
end
fprintf(fid, '%s\n','+ Out_1_OffIn12;');
if vhdl_model_par.mode_diff_enabled
if vhdl_model_par.model_name(1)=='V' % V in
fprintf(fid, [ ' Iin2 = ' verilog_tr_decomp('deltaVin2',1,model_in_out{1},'Den_Zin2','Num_Zin2') ]);
if vhdl_model_par.mode_diff_enabled
fprintf(fid, verilog_tr_decomp('deltaVin1',1,model_in_out{1},'Den_Zin_diff1','Num_Zin_diff1'));
end
else
fprintf(fid, [ ' Vin2 = ' verilog_tr_decomp('deltaIin2',1,model_in_out{1},'Num_Zin2','Den_Zin2') ]);
if vhdl_model_par.mode_diff_enabled
fprintf(fid, verilog_tr_decomp('deltaIin1',1,model_in_out{1},'Num_Zin_diff1','Den_Zin_diff1'));
end
end
if vhdl_model_par.rev_trfunction
for i=1:no
if vhdl_model_par.model_name(3)=='V' % V out
fprintf(fid, verilog_tr_decomp(['deltaIout1_' num2str(i)],i,model_in_out{i},'Num_TF_inv3','Den_TF_inv3'));
if vhdl_model_par.mode_diff_enabled_out
fprintf(fid, verilog_tr_decomp(['deltaIout2_' num2str(i)],i,model_in_out{i},'Num_TF_inv4','Den_TF_inv4'));
end
else
fprintf(fid, verilog_tr_decomp(['deltaVout1_' num2str(i)],i,model_in_out{i},'Num_TF_inv3','Den_TF_inv3'));
if vhdl_model_par.mode_diff_enabled_out
fprintf(fid, verilog_tr_decomp(['deltaVout2_' num2str(i)],i,model_in_out{i},'Num_TF_inv4','Den_TF_inv4'));
end
end
end
end
fprintf(fid, '%s\n','+ Out_1_OffIn22;');
end
fprintf(fid, '\n');
fprintf(fid, 'end \n');
fprintf(fid, 'endmodule \n');
fprintf(fid, '%s\n', '');
fclose(fid);
msgbox('Successfuly exported CADENCE VERILOG-A model!','Export','help');
edit(filepath_vhd);
end
