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Sequential AC-DC load flow method for two-terminal HVDC networks

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A HVDC load flow algorithm in Simulink treated separately from an AC load flow in SimPowerSystems.

LF_ACDC_solve.m
% File : LF_ACDC_solve.m
% By:  Silvano Casoria
% Version: 1.0
% Description: Script file for sequencial AC and DC load flow execution for
%              the "power_LFnetwork_29bus_DC.mdl" network model.
% 
disp('-------------- S T A R T -----------------');
disp('Open AC-DC network model & DC load flow solution calculation model...');
pause (1);
open ('LF_AC29bus_HVDCdemo');
open('LF_HVDC_2terminal');

ModelName='LF_AC29bus_HVDCdemo';

CHA = input('==> Start sequential load flow execution (y/n) ?: ','s');
if (CHA == 'y')
else
    break
end

% Execute the parameter initialization for the DC load flow
disp('Initialization of the DC load flow by loading the LF_HVDC_2terminal_INI ...');
LF_HVDC_2terminal_INI;
pause (1);

% Initial values for the DC load flow:
Eac_R = 735;     % (kV) 
Eac_I = 735;     % (kV)
TAPINI_R = 1.0;  % (pu)
TAPINI_I = 1.0;  % (pu)

DC_max_iter = 30;   % Maximum number of DC iterations
AC_max_iter = 30;   % Maximum number of DC iterations
Nmax  = 10;         % Maximum number of AC and DC loadflows

for i=1:Nmax
    
    % Execute the DC load flow :
    
    fprintf('////// Execute the DC load flow (Iteration No %d) //////\n',i);
    disp('INPUTS (from AC load flow): ')
    fprintf('Rectifier AC voltage: Eac_R = %5.1f kV\n', Eac_R);
    fprintf('Inverter  AC voltage: Eac_I = %5.1f kV\n\n', Eac_I);
    disp('...');
    
    sim('LF_HVDC_2terminal');  
   
    if (DC_iter(end) < DC_max_iter)
        disp(['--> DC converge after ', num2str(DC_iter(end)),' iteration(s)']);
    else
        disp(['--> Does not converge after ', num2str(DC_max_iter),' iterations)']);
    end
    
    disp('OUTPUTS (to AC load flow): ')
    
    fprintf('Rectifier P and Q: Pac_R = %7.2f MW, Qac_R = %6.2f Mvar\n',Pac_R(end),Qac_R(end));
    fprintf('Inverter  P and Q: Pac_I = %7.2f MW, Qac_I = %6.2f Mvar\n',Pac_I(end),Qac_I(end));
  
    
    
    %% Load Flow AC
    Prec=Pac_R(end);    % AC active power at rectifier (MW)
    Qrec=Qac_R(end);    % AC reactive power at rectifier (Mvar)
    Pinv=Pac_I(end);    % AC active power at inverter (MW)
    Qinv=Qac_I(end);    % AC reactive power at inverter (Mvar)
    
    set_param('LF_AC29bus_HVDCdemo/REC','ActiveReactivePowers', sprintf('[%g %g ]',Prec*1e6 , Qrec*1e6));
    set_param('LF_AC29bus_HVDCdemo/INV','ActiveReactivePowers', sprintf('[%g %g ]',Pinv*1e6 , Qinv*1e6));
      
    disp(' ');
    fprintf('////// Execute the AC load flow (Iteration No %d) //////\n',i);
    disp('...');
    LF=power_loadflow('-v2',ModelName,'solve');
 
    ibus_rec=strmatch('LG27',char(LF.bus.ID));
    ibus_inv=strmatch('MTL7',char(LF.bus.ID));
    AC_iter = LF.iterations;           % Number of AC iterations

  
    if (AC_iter < AC_max_iter)
        disp(['--> AC converge after ', num2str(AC_iter),' iteration(s)']);
    else
        disp(['--> AC does not converge after ', num2str(AC_max_iter),' iterations)']);
    end
    
    fprintf('Rectifier at %s: P = %6.2f MW, Q = %6.2f Mvar, V = %4.3f pu %6.2f deg\n',...
          LF.bus(ibus_rec).ID, Prec, Qrec, abs(LF.bus(ibus_rec).Vbus),angle(LF.bus(ibus_rec).Vbus)*180/pi)
    fprintf('Inverter  at %s: P = %7.2f MW, Q = %6.2f Mvar, V = %4.3f pu %6.2f deg\n\n',...
          LF.bus(ibus_inv).ID, Pinv, Qinv,abs(LF.bus(ibus_inv).Vbus),angle(LF.bus(ibus_inv).Vbus)*180/pi)   
    pause (1);  
    % Test for convergence of AC and DC :
    if (TAPINI_R == Tap_pu_R(end) && TAPINI_I == Tap_pu_I(end))
        disp(['AC and DC loadflows have converged after ', num2str(i), ' (AC and DC) loadflow(s)']);
        fprintf('The final values are: \n');
        fprintf('Rectifier: Tap = %5.4f (pu), alpha = %4.2f (deg), Vdc = %5.2f (kV), Pdc = %6.2f (MW)\n',...
            Tap_pu_R(end), alpha_R(end), Vdc_R(end), Pdc_R(end));
        fprintf('Inverter : Tap = %5.4f (pu), alpha = %5.2f (deg), gamma = %4.2f (deg), Vdc = %5.2f (kV), Pdc = %7.2f (MW)\n\n',...
            Tap_pu_I(end), alpha_I(end),gamma_I(end), Vdc_I(end), Pdc_I(end));
    
    % Set the PQ loads to zero (practicaly removed from the circuit) after the final
    % convergence.
       
    set_param('LF_AC29bus_HVDCdemo/REC','ActiveReactivePowers', sprintf('[%g %g ]',0 , 0));
    set_param('LF_AC29bus_HVDCdemo/INV','ActiveReactivePowers', sprintf('[%g %g ]',0 , 0));
        
        disp('======== N O R M A L  E N D I N G =========');
        return
    end
        
    % Write variables, for the next DC load flow
    Eac_R = abs(LF.bus(ibus_rec).Vbus) * 735;  % (kV)
    Eac_I = abs(LF.bus(ibus_inv).Vbus) * 735;  
    TAPINI_R = Tap_pu_R(end);  % (pu)
    TAPINI_I = Tap_pu_I(end); 
    
end
disp(['AC and DC loadflows have not converged after ', num2str(Nmax), ' (AC and DC) loadflows']);
disp('  ');
disp('======== A B N O R M A L  E N D I N G =========');


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