Accelerating Functional Verification and RTL Testbench Development with MATLAB and Simulink

Overview

As digital designs increase in complexity, there is a corresponding increase in the verification effort required. Traditional verification methods become increasingly time prohibitive and unmanageable. By using shift-left verification methods, design and verification teams can shorten verification cycles through greater use of simulation and verification at higher levels of abstraction.

In this webinar, we will show you how HDL Verifier is used with MATLAB and Simulink in workflows that enable early testing and automated generation of test environments to shorten verification testbench development.

Highlights

Concepts of Model Based Design for design verification
Shifting Left and reuse of MATLAB and Simulink testbenches
Generating DPI-C for use with HDL simulators from Cadence, Siemens, Synopsys, and AMD Xilinx
Generating UVM components and environments

About the Presenter

Mark Lin is an advanced application engineer specializing in digital design verification workflows for ASICs and FPGAs. Mark was a verification engineer at Broadcom for eight years, where he developed full-chip test environments. He earned a B.S. degree in electrical engineering from California State University of Los Angeles.

This event is part of a series of related topics. View the full list of events in this series.

Accelerating Functional Verification and RTL Testbench Development with MATLAB and Simulink

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