Overview
A significant amount of time in FPGA and SoC design verification is spent creating testbenches, running tests, and debugging designs. Spending more time in early verification in Model-Based Design helps eliminate a lot of issues, but details introduced during hardware implementation can introduce or expose bugs. This session covers how to verify and debug your design using Simulink, either by linking to an HDL simulator via cosimulation or to an FPGA board via Ethernet.
Highlights
- Verify existing RTL designs through cosimulation with HDL simulators or development boards
- Interact with free-running FPGA designs using MATLAB, including capturing data and accessing AXI4-accessible memories
- Deploy and validate algorithms using popular Zynq-based boards
About the Presenter
Curie Chung is a principal application engineer at MathWorks, where she works with customers in aerospace, communications, semiconductors, and other industries developing ASIC and FPGA projects. Previously, she was a senior software engineer at MathWorks and an electrical engineer with L-3 Communications, Security, and Detection Systems. Curie earned a B.S. degree in electrical engineering from the University of Michigan and an M.S. degree in electrical engineering from Stanford University.
