Overview
Learn about generating HDL code from MATLAB code and Simulink models for FPGA and ASIC implementation. This session starts with a brief introduction to Model Based Design and the hardware development workflow. A MathWorks engineer will then demonstrate the step-by-step process with HDL Coder to start from initial models, incorporate hardware-specific constructs, and generate Verilog and VHDL code for FPGAs and ASICs.
Highlights
- Using Simulink and Model Based Design for hardware development.
- Converting floating-point to fixed-point for hardware implementation
- Incorporating MATLAB code into HDL workflows using Simulink
- Prototyping designs on FPGA and SoC development boards
About the Presenter
Curie Chung is a principal application engineer at MathWorks, where she works with customers in aerospace, communications, semiconductors, and other industries developing ASIC and FPGA projects. Previously, she was a senior software engineer at MathWorks and an electrical engineer with L-3 Communications, Security, and Detection Systems. Curie earned a B.S. degree in electrical engineering from the University of Michigan and an M.S. degree in electrical engineering from Stanford University.
