Decode input signal using parallel concatenated decoding scheme
Convolutional sublibrary of Error Detection and Correction
The Turbo Decoder block decodes the input signal using a parallel concatenated decoding scheme. The iterative decoding scheme uses the a posteriori probability (APP) decoder as the constituent decoder, an interleaver, and a deinterleaver.
The two constituent decoders use the same trellis structure and decoding algorithm.
The previous block diagram illustrates that the APP decoders (labeled as SISO modules in the previous image) output an updated sequence of log-likelihoods of the encoder input bits, π(u;O). This sequence is based on the received sequence of log-likelihoods of the channel (coded) bits, π(c;I), and code parameters.
The decoder block iteratively updates these likelihoods for a fixed number of decoding iterations and then outputs the decision bits. The interleaver (π) that the decoder uses is identical to the one the encoder uses. The deinterleaver (π-1) performs the inverse permutation with respect to the interleaver. The decoder does not assume knowledge of the tail bits and excludes these bits from the iterations.
This block accepts an M-by-1 column vector input signal and outputs an L-by-1 column vector signal. For a given trellis, L and M are related by:
M = decoder input length
L = decoder output length
n = log2(trellis.NumOutputSymbols), for a rate 1/2 trellis, n = 2
numTails = log2(trellis.numStates) * n
The bit ordering subsystem reorganizes the incoming data into the two log likelihood ratio (LLR) streams input to the constituent decoders. This subsystem reconstructs the second systematic stream and reorders the bits so that they match the two constituent encoder outputs at the transmitter. This ordering subsystem is the inverse of the reordering subsystem at the turbo encoder.
Trellis structure of constituent convolutional code.
Specify the trellis as a MATLAB® structure that contains the trellis description of the constituent convolutional code. Alternatively, use the poly2trellis function to create a custom trellis using the constraint length, code generator (octal), and feedback connection (octal).
The default structure is the result of poly2trellis(4, [13 15], 13).
Specify the source of the interleaver indices as
When you set this parameter to
Property, the block uses
the Interleaver indices parameter to specify the interleaver
When you set this parameter to
Input port, the block uses
the secondary input port, IntrInd, to specify the interleaver indices.
Specify the mapping that the Turbo encoder block uses to permute the input bits as a
column vector of integers. The default is
(64:-1:1).'. This mapping
is a vector with the number of elements equal to L, the length of the
output signal. Each element must be an integer between 1 and L, with
no repeated values.
Specify the decoding algorithm that the constituent APP decoders use to decode the
input signal as
Max. When you set this parameter to:
True APP – the block implements true a
posteriori probability decoding
Max – the block
uses approximations to increase the speed of the computations.
Specify the number of bits which the constituent APP decoders must use to scale the
input data to avoid losing precision during computations. The decoder multiplies the
input by 2^Number of scaling bits and divides the pre-output by the
same factor. The value for this parameter must be a scalar integer between
8. This parameter only applies when you
set Decoding algorithm to
Specify the number of decoding iterations the block uses. The default is
6. The block iterates and provides updates to the log-likelihood
ratios (LLR) of the uncoded output bits. The output of the block is the hard-decision
output of the final LLR update.
Specify if the block simulates using
Code generation or
Interpreted execution. The default is
|Port||Supported Data Types|
For an example that uses the Turbo Encoder and Turbo Decoder blocks, see the Parallel Concatenated Convolutional Coding: Turbo Codes example.
 Berrou, C., A. Glavieux, and P. Thitimajshima. "Near Shannon limit error correcting coding and decoding: turbo codes,” Proceedings of the IEEE International Conference on Communications, Geneva, Switzerland, May 1993, pp. 1064–1070.
 Benedetto, S., G. Montorsi, D. Divsalar, and F. Pollara. “ Soft-Input Soft-Output Maximum A Posterior (MAP) Module to Decode Parallel and Serial Concatenated Codes,”Jet Propulsion Lab TDA Progress Report, Vol. 42–27, Nov. 1996.
 Schlegel, Christian B. and Lance C. Perez. Trellis and Turbo Coding, IEEE Press, 2004.
 3GPP TS 36.212 v9.0.0, 3rd Generation partnership project; Technical specification group radio access network; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding (release 9), 2009-12.