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dlhdl.ProcessorConfig Class

Namespace: dlhdl

Configure custom deep learning processor

Since R2020b

Description

Use the dlhdl.ProcessorConfig class to configure a custom processor, which is then passed on to the dlhdl.buildProcessor class to generate a custom deep learning processor.

Creation

The dlhdl.ProcessorConfig class creates a custom processor configuration object that you can use to specify the processor parameters. The processor parameters are then used by the dlhdl.buildProcessor class to build and generate code for your custom deep learning processor.

dlhdl.ProcessorConfig(Name,Value) creates a custom processor configuration object, with additional options specified by one or more name-value arguments.

Properties

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System Level Properties

Reference design name, specified as a character vector

Example: 'AXI-Stream DDR memory Access : 3-AXIM'

Synthesis tool name, specified as a character vector.

Example: Xilinx Vivado

Specify the target device chip family name as a character vector

Example: 'Zynq'

Synthesis tool device name specified as a character vector. When you specify the TargetPlatform, this field is populated with the default value for that target platform.

Synthesis tool package name specified as a character vector. When you specify the TargetPlatform, this field is populated with the default value for that target platform.

Synthesis tool speed value specified as a character vector. When you specify the TargetPlatform, this field is populated with the default value for that target platform.

Example: -2

Specify the target board frequency in MHz.

Example: 220

Specify the name of the target board as a character vector.

Example: 'Xilinx Zynq ZC706 evaluation kit'

Specify the name of the bitstream whose processor configuration must be retrieved as a character vector.

Example: 'Bitstream','zcu102_single'

Top Level Properties

Specify whether the runtime input signals to the deep learning processor IP core are implemented as registers or ports.

Example: 'register

Specify whether the runtime output signals from the deep learning processor IP core are implemented as registers or ports.

Example: 'register'

Specify the deep learning processor IP core input interface option as a character vector

Example: 'register'

Specify the deep learning processor IP core output interface option as a character vector

Example: 'port'

Specify the deep learning processor IP core user interface option as a character vector

Example: 'port'

Specify the deep learning processor IP core module data type as a character vector.

Example: 'single'

Processing Module conv Properties

Use this parameter to control generation of the convolution module as a part of the deep learning processor configuration.

Use this parameter to control generation of the LRN block as a part of the convolution module of the deep learning processor configuration.

Use this parameter to control generation of the segmentation block as a part of the convolution module of the deep learning processor configuration.

This parameter is the number of parallel 3-by-3 convolution kernel threads that are a part of the conv module within the dlhdl.ProcessorConfig object. To set the ConvThreadNumber to 256 the ProcessorDataType parameter must be set to int8 data type.

This parameter is a 3D matrix representing input image size limited by the conv module BRAM size within the dlhdl.ProcessorConfig object.

This parameter is a 3D matrix representing output image size limited by the conv module BRAM size within the dlhdl.ProcessorConfig object.

This parameter is a positive integer representing the maximum input and output feature size as a part of the conv module within the dlhdl.ProcessorConfig object.

Processing Module fc Properties

Use this parameter to control generation of the fully connected module as a part of the deep learning processor configuration.

Use this parameter to control generation of the Softmax block as a part of the fully connected module of the deep learning processor configuration. When you set this property to off, the Softmax layer is still implemented in software.

This parameter is the number of parallel fc MAC threads that are a part of the fc module within the dlhdl.ProcessorConfig object. To set the FCThreadNumber to 32 or 64 the ProcessorDataType parameter must be set to int8 data type.

This parameter is an unsigned integer representing cache BRAM size limited by the fc module BRAM size within the dlhdl.ProcessorConfig object.

This parameter is an unsigned integer representing cache BRAM size limited by the fc module BRAM size within the dlhdl.ProcessorConfig object.

Processing Module custom Properties

Use this parameter to control generation of the adder module as a part of the deep learning processor configuration.

Use this parameter to control generation of the addition layer as a part of the custom module of the deep learning processor configuration.

Use this parameter to control generation of the mish layer as a part of the custom module of the deep learning processor configuration.

Use this parameter to control generation of the multiplication layer as a part of the custom module of the deep learning processor configuration.

Use this parameter to control generation of the resize2d layer as a part of the custom module of the deep learning processor configuration.

Use this parameter to control generation of the sigmoid layer as a part of the custom module of the deep learning processor configuration.

Use this parameter to control generation of the swish layer as a part of the custom module of the deep learning processor configuration.

Use this parameter to control generation of the tanh layer as a part of the custom module of the deep learning processor configuration.

This parameter is an unsigned integer representing cache BRAM size limited by the adder module BRAM size within the dlhdl.ProcessorConfig object.

This parameter is an unsigned integer representing cache BRAM size limited by the adder module BRAM size within the dlhdl.ProcessorConfig object.

Methods

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Examples

Create a ProcessorConfig Object

Create a custom processor configuration. Save the ProcessorConfig object to hPC.

hPC = dlhdl.ProcessorConfig

The result is:

hPC = 
                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 200
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''

Modify Properties of ProcessorConfig Object

Modify the TargetPlatform, SynthesisTool, and TargetFrequency properties of hPC.

hPC.TargetPlatform = 'Xilinx Zynq ZC706 evaluation kit';
>> hPC.SynthesisTool = 'Xilinx Vivado';
>> hPC.TargetFrequency = 180;
hPC

The result is:

hPC = 
                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq ZC706 evaluation kit'
                             TargetFrequency: 180
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq'
                     SynthesisToolDeviceName: 'xc7z045'
                    SynthesisToolPackageName: 'ffg900'
                     SynthesisToolSpeedValue: '-2'

Retrieve ProcessorConfig object for zcu102_single bitstream

Retrieve the ProcessorConfig object for the zcu102_single bitstream and store the object in hPC.

hPC = dlhdl.ProcessorConfig('Bitstream','zcu102_single')

The result is:

hPC = 
                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'on'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 220
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''

Set the ProcessorConfig object module data type to int8

Create a custom processor configuration. Save the ProcessorConfig object to hPC.

hPC = dlhdl.ProcessorConfig

Modify the ProcessorDataType to int8.

hPC.ProcessorDataType = 'int8'

The result is:

hPC = 
                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'int8'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 200
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''

Version History

Introduced in R2020b