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Reference Design Parameters

This page describes the configuration parameters in the Reference Design Settings section of the HDL Code Generation > Target pane of the Configuration Parameters dialog box. To enable these parameters, set Workflow to IP Core Generation and set Target Platform to any non-generic platform. Use the parameters in this section to configure your custom reference design.

Reference Design

Specify the reference design with which to integrate the generated IP core. To learn more about creating a custom board and reference design, see Board and Reference Design Registration System.

The available settings depend on the value of the Target Platform parameter. Select the reference design from the drop-down menu options.

Command-Line Information

Property: ReferenceDesign
Type: character vector
Value: A valid reference design
Default: ''

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to set a reference design for the symmetric_fir subsystem inside the sfir_fixed model, use either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir','ReferenceDesign','Default system with AXI4-Stream interface')
  • Use hdlset_param to set the parameter on the model, then generate the HDL code using makehdl.

    hdlset_param('sfir_fixed','ReferenceDesign','Default system with AXI4-Stream interface')
    makehdl('sfir_fixed/symmetric_fir')

Reference design tool version

Displays the current reference design tool version. Use a reference design tool version that is compatible with the supported tool version. If there is a tool version mismatch, HDL Coder™ generates an error.

Ignore tool version mismatch

Generate a warning instead an of an error when there is a reference design tool version mismatch.

Settings

Default: Off

On

Generate a warning for a reference design tool version mismatch. You can attempt to continue creating the reference design project.

Off

Generate an error for a reference design tool version mismatch.

Reference design parameters

List of the parameters for the reference design. These parameters are the parameters available for the default reference designs that HDL Coder supports or the parameters that you define for your custom reference design. For more information, see Define Custom Parameters and Callback Functions for Custom Reference Design.

The Reference Design parameter determines the available reference design parameters. Note that the Reference design parameters table requires a string input typed directly into the Value box. These are the main reference design parameters:

  • FPGA Data Capture (HDL Verifier required): Generate and integrate the data capture IP into your reference design. Use FPGA data capture to observe signals from your design while the design is running on the FPGA. This parameter captures a window of signal data from the FPGA and returns the data to MATLAB® or Simulink® over a JTAG or Ethernet connection. To capture data over a JTAG connection, set this parameter to JTAG. To capture data over an Ethernet connection, set this parameter to Ethernet. Then, map each signal that you want to capture to the FPGA Data Capture interface in the IP Core editor. For more information, see Set Target Reference Design.

    To use this capability, you must install the HDL Verifier™ hardware support packages. See Download FPGA Board Support Package (HDL Verifier).

  • Board IP Address: Specify the IP address of the Ethernet port on the target board as a dotted-quad value. The target IP address must be a set of four numbers consisting of integers in the range [0, 255] and separated by three dots. The default value is 192.168.0.2.

    To enable this parameter, set FPGA Data Capture (HDL Verifier required) to Ethernet.

  • Insert AXI Manager (HDL Verifier required):

    By default, HDL Coder adds the Insert AXI Manager (HDL Verifier required) parameter to all reference designs. When you set this parameter to JTAG, HDL Coder inserts the JTAG AXI Manager IP into your reference design. When you set this parameter to Ethernet, HDL Coder inserts the UDP AXI Manager IP into your reference design. For more information, see Set Target Reference Design.

    By using the AXI manager IP, you can access the AXI registers in the generated DUT IP core on a hardware board from MATLAB or Simulink through the JTAG or Ethernet connection. See also Set Up AXI Manager (HDL Verifier).