You can export a MATLAB® function as a component with a direct programming interface (DPI) for use in a SystemVerilog simulation. Wrap generated C code with a DPI wrapper that communicates with a SystemVerilog thin interface function in a SystemVerilog simulation.
For MATLAB, you generate the component using the
You must have a MATLAB Coder™ license to use this feature.
Supported MATLAB data types are converted to SystemVerilog data types, as shown in this
table. When using the
dpigen function, use the
PortsDataType property to select
Logic vector, or
vector data types.
Generated SystemVerilog Types
|Compatible C Type||Logic Vector||Bit Vector|
Depends on the fixed-point word length. If the fixed-point word length is greater than the host word size (for example, 64-bit vs. 32-bit), then this data type cannot be converted to a SystemVerilog data type by MATLAB Coder and you will get an error. If the fixed-point word length is less than or equal to the host word size, MATLAB Coder converts the fixed-point data type to a built-in C type.
The logic vector length (
The bit vector length (
The coder flattens complex signals into real and imaginary parts in the SystemVerilog component.
For example, a 4-by-2 matrix in MATLAB is converted into a one-dimensional array of eight elements in SystemVerilog. By default, the coder flattens matrices in column-major order. To change to row-major order, use the
The coder flattens structure elements into separate ports in the SystemVerilog component.
|enumerated data types|
dpigen automatically compiles the shared library
needed to run the exported DPI component in the SystemVerilog environment. The
makefile that builds the shared library has the extension
_rtw.mk. For example, for
fun.m, the make file
During compilation, the function
dpigen generates a library
function is the name of the MATLAB function you generated the DPI component from.
If you use 64-bit MATLAB on Windows, you get a 64-bit DLL, which can be used only with a 64-bit HDL simulator.
Make sure that your MATLAB version matches your HDL simulator version.
dpigen also creates a test bench. You can use this
test bench to verify that the generated SystemVerilog component is functionally
equivalent to the original MATLAB function. The generator runs your MATLAB code to save input and output data vectors for use in the test bench.
This test bench is not intended as a replacement for a system test bench for your
own application. However, you can use the generated test bench as a starting example
when creating your own system test bench.
C and header files from your algorithm, generated by MATLAB Coder
C and header files for the DPI wrapper, generated by HDL Verifier™
SystemVerilog file that exposes the component and adds control signals
SystemVerilog package file that contains all the function declarations of the DPI component
SystemVerilog test bench (with the
Data files used with the HDL simulator (with the
HDL simulator scripts, such as
*.sh (with the
All SystemVerilog code generated by function
a set of control signals and the
clk: synchronization clock
clk_enable: clock enable
reset: asynchronous reset
Initialize function is called at the beginning of the
import "DPI" function void DPI_Subsystem_initialize();
If the asynchronous reset signal is high (goes from 0 to 1),
Initialize is called again.
When simulating the DPI component in your HDL environment,
clk_enable behave as follows:
0, the DPI
output function is not executed, and the output values are not
0, the DPI output
function is executed on the positive edge of the clock signal.
1, the internal
state of the DPI component is set to its initial value. This action is
equivalent to using the
clear function in
MATLAB to update persistent variables. Then output values then
reflect the DPI component initial state and current input values. For
more details on persistent variables, see Persistent Variables.
Variable-sized arguments are not supported.
Large fixed-point numbers that exceed the system word length are not supported.
Some optimizations, such as constant folding, are not supported because they change the interface of the generated C function. For more information, see MATLAB Coder Optimizations in Generated Code (MATLAB Coder).
HDL Verifier limits matrices and vectors to one-dimensional arrays in SystemVerilog. For example, a 4-by-2 matrix in MATLAB is converted to a one-dimensional array of eight elements in SystemVerilog.
The PostCodegen callback in config objects is not supported.