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FPGA Based Monopulse Technique Workflow: Part 2 - Code Generation

This example is the second of a two-part series that will help you through the steps to generate HDL code for a monopulse technique and verify that the generated code is functionally correct. The first part of the series shows how to develop an algorithm in Simulink suitable for implementation on hardware, such as a Field Programmable Gate Array (FPGA), and how to compare the output of the fixed-point, implementation model to that of the corresponding floating-point, behavioral model.

This example uses HDL Coder™ to generate HDL code from the Simulink® model developed in part one and verifies the HDL code using the HDL Verifier™. HDL Verifier™ is used to generate a cosimulation test bench model to verify the behavior of the automatically generated HDL code. The test bench uses ModelSim® for cosimulation to verify the automatically generated HDL code.

The Phased Array System Toolbox™ Simulink blocks model operations on floating-point data and provides the behavioral reference model. This behavioral model is used to verify the results of the implementation model and the automatically generated HDL code as well.

HDL Coder™ generates portable, synthesizable Verilog® and VHDL® code for Simulink blocks that support HDL code generation.

HDL Verifier™ lets you test and verify Verilog® and VHDL® designs for FPGAs, ASICs, and SoCs. We'll verify RTL generated from our Simulink model against a test bench running in Simulink® using cosimulation with an HDL simulator.

Implementation Model

This example assumes that you have a properly setup Simulink model that contains a subsystem with a monopulse technique designed using Simulink blocks that use fixed-point arithmetic and supports HDL code generation. FPGA Based Monopulse Technique Workflow: Part 1 - Algorithm Design shows how to create such a model.

To start with a new model, run hdlsetup to configure the Simulink model for HDL code generation. Open Simulink's Model Settings to configure the Simulink model for test bench creation needed for verification. Select Test Bench under HDL Code Generation in the left panel, and check HDL test bench and Cosimulation model in the Test Bench Generation Output properties group.

Comparing Results of Implementation Model to Behavioral Model

Run the model created in the FPGA Based Monopulse Technique Workflow: Part 1 - Algorithm Design to display the results. You can run the Simulink model by clicking the Play button or calling the sim command on the MATLAB command line as shown below. Use the Time Scope blocks to compare the output frames visually.

modelname = 'SimulinkDDCMonopulseHDLWorkflowExample';
open_system(modelname);

% Ensure model is visible and not obstructed by scopes.
set(allchild(0),'Visible','off');

sim(modelname);

Code Generation and Verification

This section covers the procedure to generate HDL code for a DDC and monopulse technique and verify that the generated code is functionally correct. The behavioral model provides the reference values to ensure that the output from HDL is within tolerance limits. Based on the Simulink model setup as described above, the monopulse technique designed using fixed-point arithmetic and supports HDL code generation. Alternatively, if you start with a new model, you can run hdlsetup (HDL Coder) to configure the Simulink model for HDL code generation.

To configure the Simulink model for test bench creation, open Simulink's Model Settings, select Test Bench under HDL Code Generation in the left panel, and check HDL test bench and Cosimulation model in the Test Bench Generation Output properties group.

Model Settings

After the fixed-point implementation is verified and the implementation model produces the same results as your floating-point, behavioral model, you can generate HDL code and test bench. For code generation and test bench, set the HDL Code Generation parameters in the Configuration Parameters dialog. The following parameters in Model Settings are set under HDL Code Generation:

  • Target: Xilinx Vivado synthesis tool; Virtex7 family; Device xc7vx485t; package ffg1761, speed -1; and target frequency of 300 MHz.

  • Optimization: Uncheck all optimizations

  • Global Settings: Set the Reset type to Asynchronous

  • Test Bench: Select HDL test bench, Cosimulation model and SystemVerilog DPI test bench

HDL Code Generation and Test Bench Creation

After Simulink Model Settings have been updated, you can use HDL Coder to generate HDL Code from Simulink® to generate HDL code for the HDL Algorithm subsystem. Use HDL Verifier to generate test bench model.

% Uncomment the following two lines to generate HDL code and test bench.
% makehdl([modelname '/DDC and Monopulse HDL']);   % Generate HDL code
% makehdltb([modelname '/DDC and Monopulse HDL ']); % Generate Cosimulation test bench

Since the model has accounted for pipelining in the multiplications, and we have unchecked all optimizations, there are no extra delays added to the model. We need to compensate these delays for the floating-point, behavioral model output. This will align the output of the behavioral model with the implementation model as well as the cosimulation. A delay of ($Z^{-215}$) is added to the output of the digital comparator. This delay is added to compensate for the latency in the DDC chain. Also, out of the 220 units delay, 215 unit delays compensates for the latency in the DDC chain and 5 units in the monopulse sum and difference subsystem.

After generating HDL code and test bench a new Simulink model named gm_<modelname>_mq containing a ModelSim Simulator block is created in your working directory, which looks like this:

% To open the test bench model, uncomment the following lines of code
% modelname = ['gm_',modelname,'_mq'];
% open_system(modelname);

Launch ModelSim and run the cosimulation model to display the simulation results. You can click on the Play button on the top of Simulink canvas to run the test bench or you can do it via command window from the code below

% Uncomment the following line, to run the test bench.
% sim(modelname);

The Simulink® test bench model will populate the Questa Sim with the HDL model's signal and Time Scopes in Simulink. Below are examples of the results in Questa Sim and Simulink scopes.

The Simulink scope below shows real and imaginary parts for both the cosimulation and Design Under Test(DUT) as well as the error between them

The Simulink scopes comparing the results of the cosimulation can be found in test bench model inside the Compare subsystem, which is at the output of the DDC and Monopulse HDL_mq subsystem.

% Uncomment the following line to open the subsystem with the scopes.
% open_system([modelname,'/Compare/Assert_Sum Channel HDL'])

Summary

The generated HDL code as well as a cosimulation test bench for the Simulink subsystem were created with blocks that support HDL code generation. It showed how to setup and launch ModelSim to cosimulate the HDL code. The cosimulation is performed via ModelSim for the HDL code and comparison of results to the output generated by the HDL model. The example helped in automatically generating HDL code for a fixed-point, monopulse technique and verify the generated code in Simulink®.