Group Signal Lines into Virtual Buses

You can combine signals into a bus and then access the bus as a whole or select specific signals from the bus. A virtual Simulink^® bus is analogous to a bundle of wires held together by tie wraps. For comparison, a nonvirtual Simulink bus is analogous to a struct in C code.

Not all blocks can accept buses and some blocks implicitly convert buses to vectors. To learn which blocks support which types of buses, see Bus-Capable Blocks. To identify bus conversions, see Manage Bus-to-Vector Conversions.

How you create virtual buses differs based on the location of the signals that you want to group.

To focus on fundamental steps, these examples are simple, however, buses are most useful when you have many signals to combine.

Tip

When you open a model or create a bus, the Simulink Editor does not display bus line styles. To update the line styles, you must compile the model. On the Modeling tab of the Simulink Toolstrip, click Update Model or Run.

Group Signal Lines Within a Component

Open Model

You can group signals into a virtual bus within a component by using Bus Creator blocks.

Open the example model, which contains three blocks.

To create a bus that contains the outputs from multiple blocks, drag to select the blocks. For this example, select the Chirp Signal and Sine Wave blocks. In the action bar that appears, click Create Bus.

Simulink adds a Bus Creator block and connects the inputs to that block. The output of the Bus Creator block is a virtual bus.

To make identifying the elements of the bus easier, label the inputs to the Bus Creator block. Label the output of the Chirp Signal block by double-clicking the line and entering Chirp. Similarly, label the output of the Sine Wave block Sine.

To create a second bus that contains the first bus and the output of the Step block, drag to select the Bus Creator and Step blocks. In the action bar that appears, click Create Bus. Since the Sine and Chirp signals are elements of the input bus, Simulink creates the same bus regardless of whether your selection includes the Sine Wave and Chirp Signal blocks.

Simulink adds another Bus Creator block and connects the inputs to that block. The output of the Bus Creator block is a virtual bus that contains a nested bus.

You can nest buses to any depth. If one of the inputs to a Bus Creator block is a bus, then its output is a bus hierarchy that contains at least one nested bus.

Label the output of the Step block Step and the output of the first Bus Creator block NestedBus. Optionally, arrange the blocks to improve the readability of the model.

Connect the output of the second Bus Creator block to a Scope block and label the output TopBus. To visually identify the buses, compile the model by clicking Update Model or Run on the Modeling tab of the Simulink Toolstrip. Compiling the model updates the line styles.

Connect Multiple Output Signals to a Port

Open Model

This example shows how to group the output signals of a subsystem or model into a virtual bus using Out Bus Element blocks.

Open the example model, which contains three source blocks.

Add an Out Bus Element block to the model. An Out Bus Element block is similar to a Bus Creator block connected to an Outport block. Connect the output of the Chirp Signal block to the Out Bus Element block.

The label next to the Out Bus Element block has two parts. The first part of the label describes the bus (OutBus), and the second part of the label describes the bus element (signal1). To make identifying elements of the bus easier, rename the element by double-clicking signal1 and entering Chirp.

Ctrl+drag the Out Bus Element block twice to make two copies of the block. When copying the block this way, specify whether to create a new port or use the existing port. To create one output bus that contains all of the signals, choose Use Existing Port each time you copy the block, then connect the signals.

To create hierarchy in the output bus, use dots in the part of the label that describes the bus element. Each dot creates a new level of hierarchy. Create a nested bus named NestedBus by defining the bus elements as NestedBus.Sine and NestedBus.Step, respectively.

Alternatively, you can connect a bus to an Out Bus Element block. If other Out Bus Element blocks correspond to the same port, the bus is nested in the output bus. The part of the label that describes the bus element provides the name of this nested bus.

Inspect the bus hierarchy in the dialog box for the port by double-clicking any of the Out Bus Element blocks.

The three Out Bus Element blocks create a virtual bus at the output port of the model. To see the virtual bus, reference the model in another model or move the Out Bus Element blocks into a subsystem. The line styles update when you compile the model. To compile the model, on the Modeling tab of the Simulink Toolstrip, click Update Model or Run.

Combine Multiple Subsystem Ports into One Port

Open Model

This example shows three ways to simplify a subsystem interface by converting multiple ports and their connected signals into one port and a bus.

Open the example model, which contains two subsystems with multiple input and output ports.

Drag a selection box around the signal lines between the two subsystems. From the action bar that appears, click Create Bus.

Simulink replaces the Inport and Outport blocks in the source and destination subsystems with In Bus Element and Out Bus Element blocks.

Drag a selection box around the signal lines between the source blocks and first subsystem. From the action bar that appears, click Create Bus.

Simulink adds a Bus Creator block before the first subsystem and replaces the Inport blocks in the first subsystem with In Bus Element blocks.

Drag a selection box around the signal lines between the second subsystem and Scope blocks. From the action bar that appears, click Create Bus.

Simulink replaces the Outport blocks in the second subsystem with Out Bus Element blocks and adds a Bus Selector block after the second subsystem.

The resulting model uses virtual buses at the subsystem interfaces.