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FPGA design (mem controllers)

Memory controller pa

Controller clock frequency (MHz)

Frequency of datapath between memory interconnect and memory controller.

The clock rate used to drive transactions to the external memory. The controller clock frequency determines the overall system bandwidth for external memory that must be shared among all the masters in the model.

Settings

Default: 200

Controller data width (bits)

Set the width, in bits, of the datapath between the memory controller and the memory interconnect.

Settings

Default: 64

Bandwidth derating (%)

Model memory transaction inefficiencies specified by a derating percentage value. For every 100 clocks, memory transaction execution is paused for the number of clocks equal to Bandwidth derating. To set this parameter, measure the maximum bandwidth on your board and reflect the bandwidth derating from your board in this parameter. See an example in Analyze Memory Bandwidth Using Traffic Generators.

Settings

Default: 2.3

First write transfer latency (clocks)

Specify the delay, in clock cycles, between a write request and the start of a transfer.

This delay is the number of clock cycles between making a request to the memory controller and until it returns a response. It is reflected in the Logic Analyzer waveforms as the time that the memory controller state remains as BurstAccepted. For more information about viewing waveforms in simulation, see Buffer and Burst Waveforms.

To set this value, measure the clock cycles between the burst-request and start of transfer on your board. For instructions for extracting this information from a hardware execution, see Configuring and Querying the AXI Interconnect Monitor.

Settings

Default: 4

Last write transfer latency (clocks)

Specify the delay in clock cycles between the end of a memory transfer and the end of a write transaction.

To set this value, measure the clock cycles between the end of the burst and the completion of the transaction on your board. For instructions for extracting this information from a hardware execution, see Configuring and Querying the AXI Interconnect Monitor.

Settings

Default: 4

First read transfer latency (clocks)

Specify the delay, in clock cycles, between a read request and the start of a transfer.

This delay is the number of clock cycles between making a request to the memory controller and until it returns a response. It is reflected in the Logic Analyzer waveforms as the time that the memory controller state remains as BurstAccepted. For more information about viewing waveforms in simulation, see Buffer and Burst Waveforms.

To set this value, measure the clock cycles between the burst-request and start of transfer on your board. For instructions for extracting this information from a hardware execution, see Configuring and Querying the AXI Interconnect Monitor.

Settings

Default: 5

Last read transfer latency (clocks)

Specify the delay in clock cycles between the end of a memory transfer and the end of a read transaction.

To set this value, measure the clock cycles between the end of the burst and the completion of the transaction on your board. For instructions for extracting this information from a hardware execution, see Configuring and Querying the AXI Interconnect Monitor.

Settings

Default: 1