SoC Blockset reports: Unable to generate dtb file from given dts/dtsi files

Building the PublishCustomBoardExample for the ZCU106.

I get the following msgs (See end of text for error msg(s)):

>> hdlsetuptoolpath('Toolname', 'Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2020.1\bin\vivado.bat');

Prepending following Xilinx Vivado path(s) to the system path:

C:\Xilinx\Vivado\2020.1\bin

>> boardSupportObj = createCustomBoard;

Creating folders for the target 'Board Support for ZCU106' in the folder 'C:\Users\Andrew\Documents\MATLAB\Examples\R2021a\xilinxsoc\PublishCustomBoardExample\zcu106SoCCustomBoardSupport'...

Creating the framework for the target 'Board Support for ZCU106'...

Registering the target 'Board Support for ZCU106'...

Done.

>> soc.sdk.setupSoftwareTools('Zynq ZCU106 Custom SoC Board');

>> test(boardSupportObj,'feature', 'deployment');

======================================================================

Testing: Deployment

########## Testing: Deployment ( FPGA Model and DUT Blocks ) ##########

########## Testing: Deployment ( Required MathWorks products and vendor tools ) ##########

########## Testing: Deployment ( Model compilation ) ##########

Using a new automatically generated map because no map existed.

########## Testing: Deployment ( Build Info ) ##########

### Using the SoC system information from 'C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\socsysinfo.mat'

########## Testing: Deployment ( Generate external mode model ) ##########

### Generating software system mSoCRamp_sw

### Generated software system : C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\mSoCRamp_sw.slx.

########## Testing: Deployment ( Generate IPCore for blockSubsystem) ##########

---------- Generating IPCore for mSoCRamp_fpga/Subsystem ----------

### Workflow begin.

### Loading settings from model.

### ++++++++++++++ Task Generate RTL Code and IP Core ++++++++++++++

### Generating HDL for 'mSoCRamp_fpga/Subsystem'.

### Using the config set for model mSoCRamp_fpga for HDL code generation parameters.

### Running HDL checks on the model 'mSoCRamp_fpga'.

### Begin compilation of the model 'mSoCRamp_fpga'...

### Applying HDL optimizations on the model 'mSoCRamp_fpga'...

### 'AdaptivePipelining' is set to 'Off' for the model. 'AdaptivePipelining' inserts pipeline registers at input or output or both ports of certain blocks to create patterns that efficiently map blocks to DSP units on the target FPGA device. To enable adaptive pipelining, please set the option to 'On'.

### 'LUTMapToRAM' is set to 'On' for the model. This option is used to map lookup tables to a block RAM in hardware. To disable pipeline insertion for mapping lookup tables to RAM, please set the option to 'Off'.

### Begin model generation.

### Model generation complete.

### Begin VHDL Code Generation for 'mSoCRamp_fpga'.

### Working on mSoCRamp_fpga/Subsystem/Test Source/Counter as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_src_Counter.vhd.

### Working on mSoCRamp_fpga/Subsystem/Test Source as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_src_Test_Source.vhd.

### Working on mSoCRamp_fpga/Subsystem as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_src_Subsystem.vhd.

### Code Generation for 'mSoCRamp_fpga' completed.

### Creating HDL Code Generation Check Report subsystem_ip_src_Subsystem_report.html

### HDL check for 'mSoCRamp_fpga' complete with 0 errors, 0 warnings, and 2 messages.

### HDL code generation complete.

### Begin IP core generation.

### Begin VHDL Code Generation for 'mSoCRamp_fpga'.

### Working on subsystem_ip/subsystem_ip_reset_sync as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_reset_sync.vhd.

### Working on subsystem_ip/subsystem_ip_dut as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_dut.vhd.

### Working on subsystem_ip/subsystem_ip_axi4_stream_0_master/subsystem_ip_fifo_data_OUT/subsystem_ip_fifo_data_OUT_classic/subsystem_ip_SimpleDualPortRAM_generic as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_SimpleDualPortRAM_generic.vhd.

### Working on subsystem_ip/subsystem_ip_axi4_stream_0_master/subsystem_ip_fifo_data_OUT as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_fifo_data_OUT.vhd.

### Working on subsystem_ip/subsystem_ip_axi4_stream_0_master/subsystem_ip_fifo_TLAST_OUT/subsystem_ip_fifo_TLAST_OUT_classic/subsystem_ip_SimpleDualPortRAM_singlebit as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_SimpleDualPortRAM_singlebit.vhd.

### Working on subsystem_ip/subsystem_ip_axi4_stream_0_master/subsystem_ip_fifo_TLAST_OUT as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_fifo_TLAST_OUT.vhd.

### Working on subsystem_ip/subsystem_ip_axi4_stream_0_master as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_axi4_stream_0_master.vhd.

### Working on subsystem_ip/subsystem_ip_axi_lite/subsystem_ip_addr_decoder as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_addr_decoder.vhd.

### Working on subsystem_ip/subsystem_ip_axi_lite/subsystem_ip_axi_lite_module as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_axi_lite_module.vhd.

### Working on subsystem_ip/subsystem_ip_axi_lite as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip_axi_lite.vhd.

### Working on subsystem_ip as C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\subsystem_ip.vhd.

### Code Generation for 'mSoCRamp_fpga' completed.

### HDL code generation complete.

### Generated logfile: C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\hdlcoder\Subsystem\hdlsrc\mSoCRamp_fpga\workflow_task_VivadoIPPackager.log

### Task "Vivado IP Packager" successful.

###

****** Vivado v2020.1 (64-bit)

**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020

**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020

** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source vivado_ip_package.tcl -notrace

INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.

Current project path is 'C:/Users/Andrew/AppData/Local/Temp/tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23/soc_prj/hdlcoder/Subsystem/ipcore/subsystem_ip_v1_0/prj_ip'

INFO: [IP_Flow 19-234] Refreshing IP repositories

INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Andrew/AppData/Local/Temp/tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23/soc_prj/hdlcoder/Subsystem/ipcore'.

WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'c:/Users/Andrew/AppData/Local/Temp/tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23/soc_prj/hdlcoder/Subsystem/ipcore' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'c:/Users/Andrew/AppData/Local/Temp/tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23/soc_prj/hdlcoder/Subsystem/ipcore/subsystem_ip_v1_0/prj_ip'.)

INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.1/data/ip'.

INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Stream_0_Master' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).

INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).

INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).

INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_RESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).

INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).

INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).

INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.

INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_RESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.

INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'AXI4_Lite'.

INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'AXI4_Lite_ARESETN'.

INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_CLK': Added interface parameter 'ASSOCIATED_RESET' with value 'IPCORE_RESETN'.

WARNING: [IP_Flow 19-3158] Bus Interface 'AXI4_Stream_0_Master': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.

WARNING: [IP_Flow 19-5661] Bus Interface 'IPCORE_CLK' does not have any bus interfaces associated with it.

INFO: [IP_Flow 19-2181] Payment Required is not set for this core.

INFO: [IP_Flow 19-2187] The Product Guide file is missing.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_src_Counter.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_src_Counter.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_src_Test_Source.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_src_Test_Source.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_src_Subsystem.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_src_Subsystem.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_reset_sync.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_reset_sync.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_dut.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_dut.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_SimpleDualPortRAM_generic.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_SimpleDualPortRAM_generic.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_fifo_data_OUT.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_fifo_data_OUT.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_SimpleDualPortRAM_singlebit.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_SimpleDualPortRAM_singlebit.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_fifo_TLAST_OUT.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_fifo_TLAST_OUT.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_axi4_stream_0_master.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_axi4_stream_0_master.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_addr_decoder.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_addr_decoder.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_axi_lite_module.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_axi_lite_module.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_axi_lite.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip_axi_lite.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip.vhd" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.

WARNING: [IP_Flow 19-1971] File named "hdl/vhdl/subsystem_ip.vhd" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.

INFO: [Common 17-206] Exiting Vivado at Sat Sep 18 21:50:36 2021...

Elapsed time is 19.7032 seconds.

### Workflow complete.

########## Testing: Deployment ( Create project ) ##########

---------- Generating Xilinx Design Tcl File ----------

---------- Generating constraints file ----------

---------- Creating Vivado project ----------

########## Starting bitstream generation (30-60 min) ##########

---------- Building Vivado project with 6 parallel jobs ----------

### Using the SoC system information from 'C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23\soc_prj\socsysinfo.mat'

########## Testing: Deployment ( Test Connection ) ##########

ans =

logical

1

### Skip operating system verification ...

########## Testing: Deployment ( Load Bitstream ) ##########

### Skip operating system verification ...

gmake: Entering directory `C:/Users/Andrew/AppData/Local/Temp/TPFEDD~1/soc_prj/dts'

[Pre-processing]

gmake: Leaving directory `C:/Users/Andrew/AppData/Local/Temp/TPFEDD~1/soc_prj/dts'

================================================================================

Assertion failed in soc.sdk.verify.Deployment[bsName=BoardSupportForZCU106#ext,hwName=ZynqZCU106CustomSoCBoard#ext]/testDeployment and it did not run to completion.

----------------

Test Diagnostic:

----------------

Error validating Deployment ( Load Bitstream )

Details: Unable to generate dtb file from given dts/dtsi files. Provide corresponding board dts/dtsi files during Custom Target creation and rerun the socBuilder.

Reproduction Steps: 1. Add C:\ProgramData\MATLAB\SupportPackages\R2021a\toolbox\soc\supportpackages\sdk\testmodels to MATLAB path

2. Open mSoCRamp

3. From the Apps Gallery, select System On Chip (SoC) and set Hardware Board to Zynq ZCU106 Custom SoC Board

4. Click on Configure Build & Deploy and step through the screens

------------------

Stack Information:

------------------

In C:\ProgramData\MATLAB\SupportPackages\R2021a\toolbox\soc\supportpackages\sdk\+soc\+sdk\+verify\errorFree.p (errorFree) at 0

In C:\ProgramData\MATLAB\SupportPackages\R2021a\toolbox\soc\supportpackages\sdk\+soc\+sdk\+verify\Deployment.p (Deployment.testDeployment) at 0

================================================================================

Warning: Deletion of "C:\Users\Andrew\AppData\Local\Temp\tpfeddb2b6_dd30_4cd0_ba6d_9fcc5f0b8b23" failed. Caused by:

No directories were removed.

======================================================================

Failure Summary:

Name Failed Incomplete Reason(s)

==========================================================================================================================================================

soc.sdk.verify.Deployment[bsName=BoardSupportForZCU106#ext,hwName=ZynqZCU106CustomSoCBoard#ext]/testDeployment X X Failed by assertion.

======================================================================

Features Results

______________ __________

{'Deployment'} {'Failed'}

======================================================================

Test Results Log

>>

[Kishor Akkala]

Hi Andrew,

1. Pleae provide the following information to debug further

• As mentioned in step-7 of Custom board example , are you using OS image from MathWorks GitHub repository? or using your own OS image?
• Can you share your Linux boot log
• If possible can you share your dtb file ? ( FYI.. This will be available sd card boot partition.)

2. Meanwhile can you try the following steps

By default device tree blob(DTB) will be generated using device tree information from Linux OS running on the hardware board. If possible can you try step-3 in Custom board example , I mean generating DTB using device tree files. Run the below steps and re-create the custom board.

1. Download premade device tree files from the Analog Devices GitHub repository. Copy zynqmp-zcu106-revA.dts, zynqmp.dtsi, zynqmp-clk.dtsi, and zynqmp-clk-ccf.dtsi to the current working folder.
2. Specify these files in the defineBoardSupportFiles function of the createCustomBoard script included with this example.
3. Run below command in MATLAB command window
4. boardSupportObj = createCustomBoard;
5. soc.sdk.setupSoftwareTools('Zynq ZCU106 Custom SoC Board')
6. test(boardSupportObj);

Regards,

Kishor Akkala

[Andrew Brennan]

Hi Kishor,

Sorry only just noticed this - problem was a rookie mistake (mine).

Cloned files from repository and every thing seems to build now.

Thanks

Andrew

[Aravind Mishra]

Hi Andrew,

I am struggling with the exact same problem on zcu106. I've tried building using petalinux, tried using mathworks buildroot provided image, tried custom board creation in matlab with and without dts/dtsi file (tried using both from ADI & Matlab). Nothing works. Matlab 'oscustomizer' connects to the board and reports 'all SoC Blockset features are enabled'. Yet I keep getting this deployment failure, and 'can't generate dtb from provided dts/dtsi' or 'can't read the dtb from the board, plz provide correct dtb' meassages.

Could you plz share how you resolved these issues.

Thanks

Aravind