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ip core generation stuck at hdl code generation step

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i have to convert function to ip using hdl coder but while converting it stuck at HDL code generation
1.the ouput Q port has 12*12 matrix, so in HDL code genetaion i have enabled frame to sample conversion
still am facing issues but i opted Generic ASIC/FPGA it generated a .v (verilog) file
could please help me out where am going wrong or do i have enable any other things

Answers (1)

Kiran Kintali
Kiran Kintali on 15 May 2023
Would you be able to share the MATLAB Code and the Project file?
Please reach out to tech support for help.
Angela Cuadros Castiblanco
Hello Prashanthi,
In general, matrix ports at the DUT interface are not supported in the IP core generation workflow unless Frame to Sample conversion is enabled. However, generating an IP core using frame to sample conversion is not supported for the MATLAB to HDL workflow as specified in the limitations listed in:
If you have access to Simulink, you can try generating an IP core from a Simulink model with a MATLAB function block, for an example see:
Alternatively, you can manually serialize the output of your design and map the scalar ports of the streaming output to AXI4-Stream interfaces and generate an IP core. For an example see:
Hope that helps!
Prashanthi Pathipati
Prashanthi Pathipati on 31 Jul 2023
Edited: Prashanthi Pathipati on 31 Jul 2023
the problem of generating 2-D matrix as output not relsoved,so i have decided them not include them in output and i have generated an IP with axi interface.
the problem am facing when i export the IP to vivado
1.In simulation part am able to observe the desirble output values but its not synthesizable .
2.when i observed the verilog code ,the whole code is in initial block ,as in verilog initial block is ignored in synthesis
i have changed initial block to always block and sensitive list as clock still no use.
would please suggest me a way to work on this problem like how t make the ip systhesizable or the code as systhesizable.

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