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Please help me fix Digital Upconverter filter problem

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I'm working on this example:
Implement Digital Upconverter for FPGA
It works fine when I leave the Matlab parameters as they are (the output is an 18 bit number), however I want to convert the output to a 14 bit fixed-point number then the output signal immediately outputs show problems. I tried to change the output bits of the filter and use the "data type converter" block but the output signal is not as nice as the Matlab sample signal. Can someone help me to solve this problem. It is really important to me. Thank you very much.
This is the original signal at the output of Matlab's filter when the output is fixeddt(1,18,16)
And here is the signal after I try to convert the output bits to 14 bits
  1 Comment
Ho
Ho on 15 Jul 2023
Another problem is that after generating HDL, the output signals of the DDC filter are not 14-bit numbers, it has the format vector_of_std_logic_vector14(0 TO 3); -- sfix14_En9 [4]

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Answers (2)

Ho
Ho on 16 Jul 2023
Does anyone know how to solve this problem?

Bharath Venkataraman
Bharath Venkataraman on 16 Jul 2023
I was able to update the MATLAB script and model to reduce the wordlength and fraction length by 2 bits (keeping the same headroom for integer values and reducing the fractional bits). Attached are the 14 bit input model and script.
The output of the HDL and the Simulink model are 14-bit numbers, but to accommodate the throughput, a frame of 4 values is sent out at a time. The setting outputFrame on line 366 in the MATLAB file decides the size of the output. Setting outputFrame to 1 will give you scalar 14-bit output. This comes at the expense of being able to send in data once every 64 cycles (instead of once every 16 cycles) to accommodate the interpolation in the model.
  8 Comments
Ho
Ho on 24 Jul 2023
Error appeared after I changed value outputframe = 1 (line 366)
Bharath Venkataraman
Bharath Venkataraman on 27 Jul 2023
I think this error is a duplicate of another post. Please contact MathWorks support with this issue. We will try to provide a workaround while we debug and fix the problem.

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