Delay balancing failed when generating HDL code

The problem module identified in the report is the low-pass filter module shown in Figure 1.Can anyone solve this?

Answer 1

[Kiran Kintali]

It looks like you are hitting a delay balancing error due to latency in a feedback look in the model cannot be matched.

https://www.mathworks.com/help/hdlcoder/ug/latency-considerations-with-native-floating-point.html

https://www.mathworks.com/help/hdlcoder/ug/delay-balancing.html

https://www.mathworks.com/help/hdlcoder/ug/model-with-latency-to-absorb-delays.html

What release are you using? Can you share the model?

I tried to recreate the model and used R2025b to generate code with these settings and was able to generate HDL Code.

>> hdlsaveparams(gcb)
%% Set Model 'basic_nfp_25b' HDL parameters
fpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT');
hdlset_param('basic_nfp_25b', 'FloatingPointTargetConfiguration', fpconfig);
hdlset_param('basic_nfp_25b', 'HDLSubsystem', 'basic_nfp_25b');
hdlset_param('basic_nfp_25b', 'Oversampling', 50);
hdlset_param('basic_nfp_25b', 'UseFloatingPoint', 'on');

>> makehdl('basic_nfp/Subsystem')
### Working on the model basic_nfp
### Generating HDL for basic_nfp/Subsystem
### Using the config set for model basic_nfp for HDL code generation parameters.
### Running HDL checks on the model 'basic_nfp'.
### Begin compilation of the model 'basic_nfp'...
### Working on the model 'basic_nfp'...
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 1 cycles.
### Working on... GenerateModel
### Begin model generation 'gm_basic_nfp'...
### Rendering DUT with optimization related changes (IO, Area, Pipelining)...
### Model generation complete.
### Generated model saved at hdlsrc\basic_nfp\gm_basic_nfp.slx
### Begin VHDL Code Generation for 'basic_nfp'.
### MESSAGE: The design requires 50 times faster clock with respect to the base rate = 1.
### Begin VHDL Code Generation for 'Subsystem_tc'.
### Working on Subsystem_tc as hdlsrc\basic_nfp\Subsystem_tc.vhd.
### Code Generation for 'Subsystem_tc' completed.
### Working on basic_nfp/Subsystem/Biquad Filter/nfp_sub_double as hdlsrc\basic_nfp\nfp_sub_double.vhd.
### Working on basic_nfp/Subsystem/Biquad Filter/nfp_add_double as hdlsrc\basic_nfp\nfp_add_double.vhd.
### Working on basic_nfp/Subsystem/Biquad Filter/nfp_mul_double as hdlsrc\basic_nfp\nfp_mul_double.vhd.
### Working on basic_nfp/Subsystem/Biquad Filter as hdlsrc\basic_nfp\Biquad_Filter.vhd.
### Working on basic_nfp/Subsystem/nfp_gain_pow2_double as hdlsrc\basic_nfp\nfp_gain_pow2_double.vhd.
### Working on basic_nfp/Subsystem/nfp_abs_double as hdlsrc\basic_nfp\nfp_abs_double.vhd.
### Working on basic_nfp/Subsystem/nfp_relop_double as hdlsrc\basic_nfp\nfp_relop_double.vhd.
### Working on basic_nfp/Subsystem/nfp_convert_sfix_18_En17_to_double as hdlsrc\basic_nfp\nfp_convert_sfix_18_En17_to_double.vhd.
### Working on basic_nfp/Subsystem as hdlsrc\basic_nfp\Subsystem.vhd.
### Generating package file hdlsrc\basic_nfp\Subsystem_pkg.vhd.
### Code Generation for 'basic_nfp' completed.
### Generating HTML files for code generation report at index.html
### Creating HDL Code Generation Check Report Subsystem_report.html
### HDL check for 'basic_nfp' complete with 0 errors, 2 warnings, and 3 messages.
### HDL code generation complete.

Few comments on the model based on the picture shared:

Do you really need floating point, or can you use fixed point? I notice some mixed-precision types just wanted to confirm.

Use discrete sample times wherever possible; I see a mix of sample time colors.

Take advantage of pipelining features to improve frequency and timing of the generated hardware.