HDL Coder compatibility with Microchip Libero SoC v2024.1 and roadmap for Libero 2025.x support

Hello MathWorks Support,

We are evaluating MATLAB HDL Coder for use in a hardware-in-the-loop (HWIL) emulator interface targeting Microchip PolarFire (MPF300) devices using Microchip Libero SoC. Our current development environment is:

• MATLAB / Simulink: R2024b

• HDL Coder: 24.2

• Libero SoC: v2024.1

When using HDL Workflow Advisor with Libero SoC selected as the synthesis tool, Libero v2024.1 is flagged as unsupported unless “Allow unsupported version” is enabled, even though Microchip Libero SoC v2024.1 is listed as tested in MathWorks documentation for HDL Coder. We are trying to clarify official compatibility and future support expectations, as our team is planning to upgrade Libero in the near term.

Specific questions

1. Which MATLAB release(s) are officially supported for use with Libero SoC v2024.1?

2. Is MATLAB R2024b expected to fully support Libero v2024.1 if the "allow unsupported version" option is used in HDL Workflow Advisor or is support limited to specific HDL Coder workflows (e.g., Generic ASIC/FPGA only)?

3. Is Generic ASIC/FPGA the only fully supported HDL Workflow Advisor path when targeting Microchip Libero SoC v2024.1?

4. When is support anticipated for Libero SoC v2025.1 or v2025.2? And is expected to align only with MATLAB 2026x?

5. Are there known limitations or partial support for IP Core Generation with Libero SoC, even when the Libero version is listed as tested?

For custom PolarFire platforms (non-evaluation boards) implementing real-time physics / signal-processing logic for HWIL systems, does MathWorks recommend:

- Generic ASIC/FPGA workflow with manual system integration, or IP Core Generation with additional integration steps?

Switching FPGA vendors is not an option for this program, so guidance specific to the Microchip PolarFire + Libero ecosystem would be greatly appreciated.

Thank you for your support.

Best regards,

Zamraan

Answer 1

[Kiran Kintali]

Which MATLAB releases officially support Libero SoC v2024.1?

R2025a, R2025b, and R2026a officially support Libero SoC v2024.1.

Is MATLAB R2024b expected to fully support Libero v2024.1 with "Allow unsupported version"?

In R2024b, you can proceed with Libero SoC v2024.1 if you check "Allow unsupported version," but we do not guarantee it will fully work since it is not officially tested. It can be used for:

• IP Core Generation workflow
• FPGA-in-the-Loop (FIL) workflow
• Generic ASIC/FPGA workflow

Is Generic ASIC/FPGA the only fully supported workflow for Libero SoC v2024.1?

No. In R2025a, R2025b, and R2026a, the following workflows are fully supported for Libero SoC v2024.1:

• IP Core Generation workflow
• Generic ASIC/FPGA workflow
• FPGA-in-the-Loop (FIL) workflow

When is support anticipated for Libero SoC v2025.1 or v2025.2?

Libero SoC v2025.1 support is tentatively planned for R2026b. It will be available in R2026b and R2027a.

Are there known limitations for IP Core Generation with Libero SoC?

Yes, the following are known limitations:

1. AXI Stream interface support is added in R2026a
2. FPGA IO support is not present for AXI Stream interface
3. Enabled-Based Constraints are not supported for Libero SoC

For custom PolarFire platforms, which workflow is recommended?

For custom PolarFire platforms implementing real-time physics/signal-processing logic for HWIL systems:

• IP Core Generation workflow is recommended when available (R2025a+), as it provides automated integration and software interface generation
• Generic ASIC/FPGA workflow remains a viable option for full control over system integration

For R2024b users needing immediate support, Generic ASIC/FPGA with manual integration is the safer path until upgrading to R2025a or later.

[Luca]

Hello @Kiran Kintali,

It is great to learn that the upcoming R2026a will introduce better "IP Core Generation workflow" for Microchip Libero SoC / Polarfire platform, including "AXI Stream interface support".

However, as it seems there is no plan to also add "Enabled-Based Constraints" feature? How can we Microchip Polarfire developers workaround that limitation?

Complex processing paths spanning multiple clock cycles are typical in real designs. For example, I need to model an input AXI Stream interface feeding sample data to an "Enabled Subsystem", whose activation is controlled by the AXI Stream "Valid" signal. This is a common pattern described in the MathWorks documentation, for example here.

When the "Enabled Subsystem" executes by assertion of the incoming data "Valid" signal, a real world Kalman filter design needs to execute inside the Enabled Subsystem, which will inevitably span several clock cycles.

I can generate HDL code from my design (IP Core Generation workflow for "Generic Platform" since I am still on R2024b and no AXI Stream interface support for Microchip Libero SoC) and after integration in Libero SoC, run the Synthesis + Place & Route successfully.

But of course timing verification fails because no constraints file exist which tells about the multi cycle data paths that exist in my design.

If not as a clear feature in HDL Coder, how can we come up with the necessary set_multicycle_path constraint specifications that are nececcary for timing verification?

Should we attempt to parse the HDL coder generated model to discover the multi cycle paths in the design? This seems a tricky path to say the least, not sure if it is even a correct one.

But we need something, otherwise we are limited to only simple designs with single clock cycle data paths when targeting Microchip Polarfire.

Answer 2

[Kiran Kintali]

Libero SoC v2024.1 support

• Microchip Libero® SoC v2024.1 is officially supported with HDL Coder starting in MATLAB R2025a, and continues to be supported in R2025b and R2026a.
• In MATLAB R2024b, Libero SoC v2024.1 may be used by enabling “Allow unsupported version” in HDL Workflow Advisor. However, this configuration is not officially tested, so full functionality cannot be guaranteed in that release.

Supported HDL workflows

When using an officially supported MATLAB release (R2025a and later), the following HDL Coder workflows are supported with Libero SoC v2024.1:

• Generic ASIC/FPGA workflow
• IP Core Generation workflow
• FPGA‑in‑the‑Loop (FIL)

Known limitations

• AXI‑Stream interface support was added in R2026a
• FPGA I/O support for AXI‑Stream interfaces is currently not available
• Enable‑based timing constraints are not supported for Libero SoC

Libero SoC v2025.x roadmap

• Support for Microchip Libero SoC v2025.1 is planned for MATLAB R2026b, and will continue into subsequent releases.

We hope this helps with planning your toolchain upgrades. Please let us know if you have any follow‑up questions or need guidance on a specific workflow.