How to use the Unit Delay for HDL-Coder on Zedboard Zynq-7000?

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We'd like to use the standard Unit Delay block in the Simulink HDL-Coder. As a minimal example we created an Atomic Subsystem, only consisting of a single Unit Delay block.
The simulation worked as expected: The input signal was delayed by one time step.
The model was tested on our Zedboard Zynq-7000. The subsystem ran on the FPGA. However, in contrast to the simulation, the unit delay did not seem to do anything at all, as the output signal was exactly the same as the input signal.
We use Matlab R2015b with Vivado 2014.4.
The Simulink model was attached.

Accepted Answer

Wang Chen
Wang Chen on 25 Jan 2016
Hi Jan, when you run the model on Zynq board, the FPGA part of the design is running at a fast frequency (50MHz). When you are using external mode to monitor the output, the ARM processor is running at a much slower sample rate (e.g. 10KHz), the delay in FPGA happens so fast that ARM cannot see it.
You can try the coprocessing Processor FPGA synchronization mode, where the FPGA is slowed down to be locked step with ARM sample time, so you can see the delay effect.
Or you can build a small counter using the unit delay, and observe that the counter counts at fast frequency in the FPGA.
Or you can use following example to save the fast FPGA signal in a FIFO, and then bring the data back to ARM to see the delay result.

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