How to auto-generate the test cases using Simulink Design Verifier on a huge model which has unit models inside it. How can i avoid the error active configuration cannot be changed in compilation or simulation?

As per the process I have been using this Simulink design Verifier for auto generating the test cases. When I am trying to do on the HVAC module which has 20 to 25 unit models assigned to it. I am supposed to generate the test cases for the huge model which has 324 inputs and 171 outputs. Inside the HVAC module, there are many unit models which are like a reference to this huge model.

I would like to avaoid an error which is relating to the active configuration changes are not done while compilation or simulation. The stop mentioned is "inf". I have checked the configuration pane and changed the process accordingly. There is one more issue is that, when I am trying to correct the error and trie to rebuild the process, it wont start again. The error dialog box says that there is one unit model which is compiling or simulating mode.

I would like to know is their anything that I can avoid the errors to do my work.

[Shishir Dwivedi]

Hello Kameswari,

I would like to understand your use case in greater details & particularly interesed to know below mentioned queries.

• Are you getting the issue only while generating test cases from SLDV or the issue is generic even if you Compile or Build the model?
• Are you able to generate test cases for individual units, right click on subsystem(s) aka units and generate test cases?
• Are there any model call backs assigned to individual units?

As the query seems to be bit involved with your workflow, it would be great if you could create a service request ticket from this link.

Best Regards,

Shishir.

Answer 1

[Kameswari Vemuri]

Hi Shishir,

Thanks for addressing my question.

1. I face the situation only when I go with SLDV process where I want to generate the testcases for the 100's of inputs and outputs mentioned in the model. When I try to build/simulate or compile the model I do not face any problem since the stop time is Inf it runs continously with some warnings related to the model which can be handled by using the Configuration Pane. It is just with the SLDV process where I try to follow the same process of generating the testcases from the model.

2.I can generate the testcases for the unit models directly by doing the right-click on the main unit subsytem block and continuing the process or by making the model referenced and doing the same process for the whole unit model. In both the process can be handled by using the Configuration Pane.

3.Probably the whole model or the unit models has a call back and linked to each other.

[Shishir Dwivedi]

Hello Kameswari,

Thanks for the detailed response, seems the unit model callbacks are trigerring the simulation of some other unit in your workflow (they might be copuled with each other). This might require a detailed investigation, it would be great if you could create a service request ticket from this link. We can then have a detailed investiagtion at your workflow.

Best Regards,

Shishir.

[Kameswari Vemuri]

Hello,

I have already raised a service request and waiting for the response from the technical guys from your side. thanks for helping me out in this process.

Kameswari Vemuri