is it possible to work with Altera Cyclone(EP1C12Q240C8) FPGA kit and Matlab HDL workflow advisor ?

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I have
  1. Cyclone FPGA kit (EP1C12Q240C8) {with a interfacing card made by IISC Bangalore}
  2. Matlab 2011b (and Matlab 2012a)
  3. Modelsim 10.0c SE
  4. Altera Quartus II (11.0sp1) Web Edition (i.e free version)
  5. OS: Windows Xp sp2 (32bit)
I can't find out this board in "loop-in-FPGA" .
my question is that how to use this board with the help of matlab ?
  1. How to download HDL code into this FPGA kit
  2. How to map the Input and Output pins (say I want input/Output from some particular I/O pins )
With Regards

Accepted Answer

Wang Chen
Wang Chen on 28 Sep 2012
Hi Kingsuk,
Both the FPGA-in-the-loop and FPGA Turnkey workflow does not support Altera Cyclone FPGA family. The supported FPGA families include Altera Cyclone III and Cyclone IV.
You can still use HDL workflow Advisor to generate the HDL code and the Altera Quartus project. And then you need to work in the Quartus project to map the input/output pins (using constrain file or Quartus Pin Planner), generate bitstream, and use Quartus Programmer to download the bitstream to your FPGA kit.
Kingsuk on 30 Sep 2012
would you like to provide me some tutorial links for using constrain file or Quartus Pin Planner regarding this subject.
With Regards
Kingsuk on 3 Oct 2012
But a new problem is coming if I follow the above process.
in simulink model I create a simple add two number model
1. one constant block having value 4 with fixdt(0,12) 2. another constant block having value 5 with fixdt(0,12) 3. sum block with fixdt(0,13), min value =4 and Max value =9 In compare scope both result is 9 but in co-simulation (modelsim) wave format and also in Quartus it is showing 576 (unsigned format)
I can't understand the reason would you to like to give me a way to break this nutshell
With Regards Kingsuk

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More Answers (1)

Kingsuk on 3 Oct 2012
I have attached the HDL code herewith
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL;
ENTITY Addkm IS PORT( R : OUT std_logic_vector(12 DOWNTO 0) -- ufix13_En6 ); END Addkm;
-- Signals
SIGNAL A_out1 : unsigned(11 DOWNTO 0); -- ufix12_En9
SIGNAL B_out1 : unsigned(11 DOWNTO 0); -- ufix12_En9
SIGNAL Sum_add_cast : unsigned(12 DOWNTO 0); -- ufix13_En9
SIGNAL Sum_add_cast_1 : unsigned(12 DOWNTO 0); -- ufix13_En9
SIGNAL Sum_add_temp : unsigned(12 DOWNTO 0); -- ufix13_En9
SIGNAL Sum_out1 : unsigned(12 DOWNTO 0); -- ufix13_En6
BEGIN A_out1 <= to_unsigned(2048, 12);
B_out1 <= to_unsigned(2560, 12);
Sum_add_cast <= resize(A_out1, 13);
Sum_add_cast_1 <= resize(B_out1, 13);
Sum_add_temp <= Sum_add_cast + Sum_add_cast_1;
Sum_out1 <= resize(Sum_add_temp(12 DOWNTO 3), 13);
R <= std_logic_vector(Sum_out1);
END rtl;

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