HDL Coder: How to create a resettable delay that triggers on rising edge

Hello Community

I'm trying to implement a limited counter which has a variable upper limit, i.e. the upper limit is given by a signal.

This proposed solution does this. The problem is that this solution is not HDL code generation compatible. If I try to generate VHDL code, I get the follwing error from the resettable delay block:

Only 'Level' external reset mode on the Delay block is supported in 'Classic' mode.

If I set the External reset to "Level" mode, the behaviour is no longer correct.

What do I have to do in order to create a resettable delay block that behaves in the same way as a flip flop that resets on the rising edge?

Furthermore, what is the "Classic mode" in this error message? I cannot find an answer to this in the documentation.

Answer 1

[Kiran Kintali]

Please find attached two variations of the model generating HDL code.

Simulink “Counter Limited” block with dynamic upper limit

One using MATLAB function block with the following code

function y = fcn(u)

persistent count;

if isempty(count)
    count = int8(0);
end

if count > u
    count = int8(0);
end

y = count;

if count <= u
    count = count + 1;
end

end

Other using basic Simulink blocks

[Dominik Hiltbrunner]

This works very well. Thank you!