Unfortunately, for some time now I have been having problems generating a bitstream and related to that, generating a Simulink Real-Time interface block. The hardware used is a Speedgoat Performance with the module IO332-200K with the front- (21) and rear-plugin (06). As software environment I use Matlab 2019b with the latest HDL Coder Integration Package provided by Speedgoat GmbH as well as the Speedgoat library (both for Matlab 2019b). As synthesis tool I use - as also provided by Speegoat GmbH for the matching FPGA - Xilinx Vivado Design Suite - HLx Edition version 2018.3, because a test with version 2019.2 did not work.
Now more detailed to my problem:
After setting the setuptoolpath via the following command in the Matlab Command Window
and opening the HDL Workflow Advisor and setting the required "settings" as shown in the following pictures,
there is neither a warning nor an error within these two "tasks". At "1. Set Target", "2. Prepare Model for HDL Coder Generation" and "3.1. Set Code Generation Options" occured no error message or warning. But at point "3.2. Generate RTL Code and IP Core" occurred a warning even though the task runs without errors.
The complete error message reads:
[Warning: Family artix7 not characterized. Using default value, SynthesisToolChipFamily=virtex7 and SynthesisToolSpeedValue=-1, for
[> In characterization.getCharacterizationPathXilinxGeneric
If I interpret this error message correctly, the correct FPGA family Artix 7 is not recognized and therefore the HDL Workflow Advisor switched back to the Virtex 7, which in my opinion causes an error during bitstream generation.
This error subsequently manifests itself in the operation of the Speedgoat when reading the analog voltage inputs on the Speedgoat, as these now display incorrect values and in some cases have offsets.
Does someone know this problem and can help?