Design Verifier error: The model is contradictory in its current configuration. Why?

I have a large model and I'm trying to Generate Test Cases for Coverage with Simulink Design Verifier.

I didn't add any test objective or test condition blocks to the model. Just executed the tool on the model.

After 20 minuts of analysis the tool stops with the following error: "The model is contradictory in its current configuration. All objectives are Unsatisfiable/Falsifiable."

In the user guide the only reference to the problem is : "You can have a contradiction if your model has Test Objective blocks with incorrect parameters. For example, a contradiction can be an objective that states that a signal must be between 0 and 5 when the signal is the constant 10. ", but I didn't add any SLDV blocks.

The same error appears when I try to execute SLDV Design Error Detection to Check specified intermediate minimum and maximum values.

Can someone suggest me what sould I look for in the model? There are specific Simulink objects that can make my model contradictory and that I sholud check deeply?

[Pat Canny]

Hi Luigi,

This would likely require additional information on your model. Could you please contact MathWorks Technical Support?

Thanks.

- Pat