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Control Synthesis for a Surface Mount Device with Simulink Design Verifier

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Simulink Design Verifier finds a force control profile to stamp a component onto a circuit board.

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When mounting a component onto a circuit board, the component must be held against the board with a low acceleration for a specific duration. To satisfy this requirement, an appropriate control force profile must be determined.
The stamping operation comprises three modes: (i) the movement of the component toward the board, (ii) the holding against the board, and (iii) the release of the component.

In the holding mode, the numerical simulation must handle the large reaction force that is exerted by the board. This results in a time constant much faster than in the two other modes. So, the system is considered numerically stiff.

A variable step solver that is necessary to efficiently handle stiff behavior is explicitly modeled. Because the solver model is discrete, Simulink Design Verifier can be applied to the problem of finding a required control force profile.

Details about the theoretical background can be found in the article "A Computational Model of Time for Stiff Hybrid Systems Applied to Control Synthesis" by P.J. Mosterman, J. Zander, G. Hamon, and B. Denckla as published in the August 2011 issue of the IFAC journal Control Engineering Practice.

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MATLAB 7.12 (R2011a)

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