Three-Level NPC Converter SVPWM (with DC voltage balancing)

SVPWM algorithm for 3-level NPC converter with DC voltage balancing

This model is based on a study of the thesis (or book, Unfortunately the document I have do not have a title) authored by Josep Pou from the Technical University of Catalonia. No novelty is claimed here. The algorithm is based on dq-gh transformation and sextant symmetry in the SV diagram, hence simplifying sector, region and duty cycle calculations. Neutral dc voltage balancing is achieved, by implementing the NTV sequencing method with logic operations on the state feedback of the current imbalance on the DC bus due to neutral current. Note that the algorithm is performed in per unit, however if you wish to use this model for control purposes, then simply divide your dq reference values by a half of the maximum synthesis voltage (based on your DC voltage). This model is made with consideration in implementing it in labview FPGA, hence various sections of the code are optimized for digital implementation with mostly add, subtract, invert, logic and signal routing functions. If you really wish to understand this model, I strongly suggest you find the above referenced paper and study it thoroughly. Any questions will be answered when I visit the site. This is my first time uploading, any criticism are very much welcome :)