High Performance Single-Phase PLL with SFT phase detector

The Simulink model of A high-performance single-phase SFT-based PLL that gives outstanding performance is given

A high performance single-phase phase-locked loop using a sliding Fourier transform is proposed in this paper. The new PLL is using the sliding Fourier transform as a phase detector. The orthogonal signal is generated using a controlled transfer delay which is adjusted by the PLL estimated frequency. Feedback loops of the frequency and phase estimated by the PLL are used to drive the filters of the Fourier transform and to adjust the period of the transfer delay for implementing the sliding integrals. Unlike the synchronous reference frame PLL, the proposed SFT-based PLL (SFT-PLL) is adaptive to frequency changes and provides better harmonics and DC offset rejection while maintaining a constant sampling frequency. Therefore, the proposed method lends itself to digital implementation in a simple and straightforward manner. These distinguishing features allow the SFT-PLL to be especially appropriate for interfacing weak single-phase micro-grids where high harmonic distortion and frequency variations are common characteristics. A Simulink file contains the method implementation and compares it with the second-order generalized integrator phase-locked loop (SOGI-PLL) to validate the effectiveness and advantages of the proposed method under changing grid conditions. It can be easily observed that the SFT-PLL offers superior performance in almost all testing scenarios. The implementations given here is based on a continuous-time Fourier transform where the integration of signals is used instead of accumulation. The discrete form can be easily implemented by replacing integrators with accumulators and by dividing by the number of samples instead of dividing on the periodic time for the averaging process of Fourier Transform. The discrete form is, of course, more efficient regarding the number of math operations and the use of calculations resources.
The DSP implementation, however, needs special attention to deal with integrator/accumulator saturation issue. Saturation is a result of the limited capacity of numbers used by DSPs (workarounds can be advised by contacting the contributor)