Answered
"Detect Increase" causes multiple identical HDL files to be generated with HDL coder
Please consider this option to increase reuse of shared modules. https://www.mathworks.com/help/hdlcoder/ug/generating-reusab...

3 years ago | 0

Answered
Timing error happened when seting series IIR filter in Speedgoat target machine
Please reach out to tech support for guidance on the topic with your model. You can use the workflow to get a high level view o...

3 years ago | 0

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Answered
How to convert the simscape sample model('ssc_lithium_cell_1RC') to HDL
The model needs to be made Simscape HDL compliant for FPGA/HIL targeting. Watch out this space for guidance on this topic or rea...

3 years ago | 0

Answered
XADC in System Generator/Model Composer for MATLAB
Can you share your Simulink model? Are you trying to utilize HDL Coder workflow advisor IP core generation features? https:/...

3 years ago | 0

Answered
converting fixed point simulink model to zynq 706
https://www.mathworks.com/help/supportpkg/xilinxzynqbasedradio/ug/fpga-targeting-workflow.html Communications Toolbox Support P...

3 years ago | 0

Answered
Mexw64 file not found in matlab foc example
The example ships mex files only for Windows. You need to have necessary products such as Simscape in place to rebuild mex on ot...

3 years ago | 0

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Answered
Synthesis keeps on running for indefinite time on Xilinx RFSOC ZCU111
Please reach out to support if you still run into this issue.

3 years ago | 0

Answered
Can we automatically/directly convert simulink block diagram(simulink model) into MATLAB code ?
https://www.mathworks.com/products/hdl-coder.html HDL Coder supports code generation from both MATLAB and Simulink models. I ...

3 years ago | 0

Answered
error in conversion to hdl code"Persistent variable 'y' must be assigned before it is used. The only exception is a check using 'isempty(y)' that can be performed prior to assignment."
You have too much IO on the DUT. (20385 + 200)*dataWordLength ==> too many IO pins. Either you need to stream the inputs an...

3 years ago | 0

Answered
how to plot HDL cosimulink output
HDL Verifier Cosimulation Model Generation in HDL Coder https://www.mathworks.com/help/hdlcoder/ug/hdl-verifier-cosimulation-mo...

3 years ago | 0

Answered
Convert Matlab Code (.m) to Digital Circuits
Get Started with MATLAB to HDL Workflow https://www.mathworks.com/help/hdlcoder/gs/getting-started-with-matlab-to-hdl-workflo...

3 years ago | 1

Answered
Latches inferred from HDL code generated from m-code switch statement
Thank you for the reproduction model. We will try to address the issue if this is still reproducible. Can you share what version...

3 years ago | 0

Answered
Use of DSP systems toolbox and computer vision toolbox with HDL coder
You can use this command to view the HDL Comptible Blocks. >> hdllib

3 years ago | 0

Answered
HDLcoder ignores coder.const
You can find examples of HDL Coder friendly designs with coder.load and coder.const in the attachment.

3 years ago | 0

Answered
MATLAB HDL Coder build error: C compiler produced errors
You can use this helper command to copy any of the HDL Coder friendly MATLAB demo files matlab\toolbox\hdlcoder\hdlcoderdemos\ma...

3 years ago | 0

Answered
How do I find the peak of a signal and the time of peak?
Sharing HDL Coder compatible Peak Detector example here. https://www.mathworks.com/matlabcentral/fileexchange/69651-hdl-coder-s...

3 years ago | 0

Answered
RAM based circular shift register in Simulink
If you are looking to model delay length via input port using RMA you could use the following style of modeling pattern.

3 years ago | 1

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run Simscape HDL Workflow Advisor from script
Strarting R2025a pre-release Simscape HDL generates both floating-point and fixed-point enabled code generation from Simscape mo...

3 years ago | 0

Answered
dsp.fft system object unbounded in a for loop
The functions fft() and dsp.fft() do not support HDL streaming interface. You can consider using dsphdl.fft or build a custom F...

3 years ago | 0

Answered
Build Standalone application for Zynq 706
There are several product examples that show case how to deploy HDL Coder generated code to target ZC706 board. Check this exam...

3 years ago | 1

Answered
Simulink DSP Simulations with Noise: Looking for best practices
You might want to get started with this HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexch...

3 years ago | 1

Answered
Why do I get the error: " FIL cosimulation failed: the output does not match the expeced result" when I run FPGA-in-the-Loop Test?
If the HDL Code you are running is run with is generated from HDL Coder and is not matching the MATLAB or Simulink testbench the...

3 years ago | 0

Answered
dsp.FFT does not work with HDL coder
dsphdl.FFT ships with DSP HDL Toolbox. You can also find some examples of how to write custom FFT in MATLAB suitable for HDL Co...

3 years ago | 0

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Answered
I2C Master block in SOC FPGA
Please find attached a sample example of I2C Master and Slave model blocks with behavioral plant models for IMUs. You can also ...

3 years ago | 0

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Answered
how to use I2C master block in HDL Code
Please find attached a sample example of I2C Master and Slave model blocks with behavioral plant models for IMUs. You can also ...

3 years ago | 0

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Answered
How to access HDL coder in Matlab trial version for college use ?
Reach out to support team for trial/install issues.

3 years ago | 0

Answered
face this error when wanna generate HDL coder "The Block/HDLImplementation pair: ('built-in/Reference', 'Module') is not registered in the implementation database."
Please reach out to support@mathworks.com This seems to be some sort of installation issue.

3 years ago | 0

Answered
PWM IP core FPGA
You can use core Simulink blocks to build a waveform of your choice.

3 years ago | 0

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Answered
HDL QAM Transmitter and Receiver simulation problem
Please reach out to tech support for further support on this question. Thanks

3 years ago | 0

Answered
Pipelining using HDL Coder
Can you share some sample code and the project file? if the critical path is within optimized IP such as hdl.FFT distributed pi...

3 years ago | 0