Designing AI Engines of Xilinx Versal ACAP Using Simulink and Vitis Model Composer
Versal® Adaptive SoCs are Xilinx’s newest compute platform, incorporating a processing technology known as AI Engines. They can accelerate machine learning inference and advanced signal processing workloads such as beamforming, FFTs, and filters.
In this webinar, engineers from MathWorks and Xilinx will show how Simulink and Vitis Model Composer can be used to target AI Engines and programmable logic. Using a 4 giga-sample per second FIR filter as a reference example, the presenters will model, simulate and optimize their design to achieve the best system performance, implement the filter on the AI Engine array, and show how to generate a complete system.
- Introduce Xilinx Versal ACAP platform and AI Engine processing technology
- Use Simulink and Vitis Model Composer to design, simulate and optimize a 4GSPS Filter using super sample rate architecture
- Target filter design to AI Engines and programmable logic
- Show a hardware demonstration
About the Presenters
Olivier Tremois is a Technical Marketing Manager at Xilinx responsible for the AI Engine Training and developed several tutorials on AI Engine processor array. Before that, he was a DSP Specialist covering EMEA and India for 15 years. Prior to Xilinx, he worked at Thales in active and passive sonar system research and development, and he spent 5 years in a telecom startup on PHY layer implementation. He holds a PhD in Digital Signal Processing obtained in 1995.
John Pitrus is a Partner Manager at MathWorks concentrating on FPGA, ASIC and SoC workflows for general-purpose applications. Prior to MathWorks, he served in various marketing and product application roles at Analog Devices, Dell EMC and Conexant. John holds a BS in Computer Engineering from Rensselaer Polytechnic Institute and an MBA in Marketing from University of Chicago Booth School of Business.
Recorded: 27 Oct 2021
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