Simulink^®

Unit Delay - Delay signal one sample period

Library

Discrete

Description

The Unit Delay block delays its input by the specified sample period. This block is equivalent to the z^-1 discrete-time operator. The block accepts one input and generates one output, which can be either both scalar or both vector. If the input is a vector, all elements of the vector are delayed by the same sample period.

You specify the block output for the first sampling period with the Initial conditions parameter. Careful selection of this parameter can minimize unwanted output behavior. The time between samples is specified with the Sample time parameter. A setting of -1 means the sample time is inherited.

Note The Unit Delay block accepts continuous signals. When it has a continuous sample time, the block is equivalent to the Simulink^® Memory block.

The Unit Delay block provides a mechanism for discretizing one or more signals in time.

Note Do not use the Unit Delay block to create a slow-to-fast transition between blocks operating at different sample rates. Instead, use the Rate Transition block.

Data Type Support

The Unit Delay block accepts real or complex signals of any data type supported by Simulink software, including fixed-point data types. If the data type of the input signal is user-defined, the initial condition must be zero.

For a discussion on the data types supported by Simulink software, see Data Types Supported by Simulink^® in the Simulink documentation.

Parameters and Dialog Box

Initial conditions: The output of the simulation for the first sampling period, during which the output of the Unit Delay block is otherwise undefined. The Initial conditions parameter is converted from a double to the input data type offline using round-to-nearest and saturation.
Sample time (-1 for inherited): Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specifying Sample Time in the online documentation for more information.

The State Attributes pane of this block pertains to code generation and has no effect on model simulation. See Block State Storage and Interfacing in the Real-Time Workshop^® documentation for more information.

Bus Support

The Unit Delay block is a bus-capable block. The input can be a virtual or nonvirtual bus signal subject to the following restrictions:

Initial conditions must be zero or a non-zero scalar.
If Initial conditions is zero and a State name is specified, the input cannot be a virtual bus.
If Initial conditions is a non-zero scalar, no State name can be specified.

Characteristics

Bus-capable	Yes, with restrictions as noted above
Direct Feedthrough	No
Sample Time	Specified in the Sample time parameter
Scalar Expansion	Yes, of input or initial conditions
States	Yes--inherited from driving block for nonfixed-point data types.
Dimensionalized	Yes
Multidimensionalized	Yes
Zero Crossing	No