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# Symbol Synchronizer

Correct symbol timing clock skew

Synchronization

## Description

The Symbol Synchronizer block corrects for symbol timing clock skew for PAM, PSK, or QAM modulation schemes. The block accepts a single input port. To obtain a normalized estimate of the timing error, select the Normalized timing error output port check box. The block accepts a complex input signal and returns a complex output signal and a real timing error estimate. The Sym output is variable-size with maximum dimensions of $⌈\frac{{N}_{samp}}{{N}_{sps}}×1.1⌉$, where Nsamp is the number of samples and Nsps is the samples per symbol. Output that would exceed this limit is truncated. The Err output has the same dimensions as the input signal.

## Parameters

Modulation type

Specify the modulation type as PAM/PSK/QAM, or OQPSK. The default setting is PAM/PSK/QAM.

Timing error detector

Specify the timing error detector as Zero-Crossing (decision-directed), Gardner (non-data-aided), Early-Late (non-data-aided), or Mueller-Muller (decision-directed). The default setting is Zero-Crossing (decision-directed).

Samples per symbol

Specify the number of samples per symbol as a positive integer scalar greater than or equal to 2. The default setting is 2.

Damping factor

Specify the damping factor of the loop filter as a positive real finite scalar. The default setting is 1. This parameter is tunable.

Normalized loop bandwidth

Specify the normalized loop bandwidth as a real scalar between 0 and 1. The bandwidth is normalized by the sample rate of the symbol synchronizer block. The default setting is 0.01. This parameter is tunable.

### Note

Set Normalized loop bandwidth to less than 0.1 to ensure that the symbol synchronizer locks.

Detector gain

Specify the detector gain as a real positive finite scalar. The default setting is 2.7. This parameter is tunable.

Normalized timing error output port

Select this check box to provide the normalized timing error to an output port. The default for this parameter is selected.

Simulate using

Select the type of simulation to run.

• Code generation. Simulate model using generate C code. The first time you run a simulation, Simulink generates C code for the block. The C code is reused for subsequent simulations, as long as the model does not change. This option requires additional startup time but provides faster simulation speed than Interpreted execution.

• Interpreted execution. Simulate model using the MATLAB interpreter. This option shortens startup time but has slower simulation speed than Code generation.

The default setting is Code generation.

## Algorithms

This block implements the algorithm, inputs, and outputs described on the comm.SymbolSynchronizer reference page. The object properties correspond to the block parameters.

For OQPSK, the in-phase and quadrature signal components are first aligned (as in QPSK) using a buffer (state) to cache the last half symbol of the previous input. After initial alignment, the remaining synchronization processing is QPSK.

## Examples

expand all

Correct for a fixed symbol timing offset on a noisy QPSK signal.

Open the doc_symbolsync model.

Run the model. The Variable Fractional Delay block is used to introduce a timing error of 2 samples. As the Raised Cosine Transmit Filter is configured to have 4 Output samples per symbol, the timing delay is 0.5 symbols. The constellation diagram without symbol synchronization shows that the QPSK symbols cannot be successfully resolved.

The constellation diagram for the signal after the synchronizer shows that the QPSK symbols can now be resolved.

Try to experiment with the model by changing the delay and the Timing error detector algorithm.

Recover frame synchronization from a QPSK system suffering from a variable timing error.

Run the model. The Before Sym Sync and After Sym Sync constellation diagram blocks show the effects of a timing error on the transmitted QPSK constellation. This timing error is introduced as a variable delay that ranges from 0 to 0.9 samples. The Symbol Synchronizer block corrects for clock skew between a single-carrier transmitter and receiver, aligning the output data with a valid clock reference. Depending on the size of the timing error, the output dimensions of the symbol synchronizer vary. In this example, the symbol synchronizer returns a vector containing 99, 100, or 101 samples for a 100-sample input vector.

The bit error rate (BER) is calculated by the Data Decoding block. Within that block, the input data is regenerated rather than being taken from the Bit Generation block because the BER is calculated only for valid frames. The Preamble Detector finds the start of packet in the demodulated bit stream. The Frame Synchronizer uses this start index to align the bit stream along correct frame boundaries and also provides a valid frame indicator.

The signal is recovered correctly, as seen by a BER of zero (or less than 10-5) for the 20 dB signal-to-noise ratio used here.

The constellation diagram before the symbol synchronizer shows the effects of the variable timing error. Because the timing error varies over time, the constellation oscillates between corrupted and clean states.

The After Sym Sync constellation diagram shows that the synchronizer removes the effects of the variable timing error.

Experiment with the model by commenting through (Ctrl-Shift-Y) the Symbol Synchronizer block and setting the decimation factor of the Raised Cosine Receive Filter block to 2. Without symbol synchronization, the BER increases significantly because the timing error corrupts the received signal to the point that bit errors occur.

## Supported Data Types

PortSupported Data Types
Sample Input
• Double-precision floating point

• Single-precision floating point

Symbol Output
• Double-precision floating point

• Single-precision floating point

Normalized Timing Error
• Double-precision floating point

• Single-precision floating point

## References

[1] Rice, Michael. Digital Communications: A Discrete-Time Approach. Upper Saddle River, NJ: Prentice Hall, 2009, pp. 434–513.

[2] Mengali, Umberto and Aldo N. D’Andrea. Synchronization Techniques for Digital Receivers. New York: Plenum Press, 1997.