How Deep Learning HDL Toolbox Compiles the GRU Layer

R2026b

To manually deploy a gated recurrent unit (GRU) layer network to your target board, learn how the compile method of the dlhdl.Workflow object interprets the GRU layer in a network. When you compile GRU layers, Deep Learning HDL Toolbox™ splits the GRU layer into components, generates instructions and memory offsets for those components.

The compile method of the dlhdl.Workflow translates the:

• Reset gate into gru.rh

• Input and update gate into gru.wh

Then, the compile method:

• Inserts a depth concatenation layer between the layer preceding the GRU layer and the gates of the GRU layer.

• Generates sigmoid, hyperbolic tangent, multiplication, and addition layers to replace the mathematical operations of the GRU layer.

When the network has multiple stacked GRU layers, the compile method uses the GRU layer name when generating the translated instructions. For example, if the network has three stacked GRU layers named gru_1, gru_2, and gru_3, the output of the compile method is gru_1.wh, gru_1.rh, gru_2.wh, gru_2.rh, and so on. The compiler schedules the different components of the GRU layer, such as fully connected layers, sigmoid blocks, tanh blocks, and so on, into different kernels in the deep learning processor architecture.

This image shows how the compile method translates the GRU layer:

To see the output of the compile method for a GRU layer network, see Run Sequence Forecasting Using a GRU Layer on an FPGA.

Deep Learning Processor Configuration for Recurrent Layers

When you want to generate a custom bitstream for deploying a recurrent layer network, you must:

• Set the fully connected (FC) layer ModuleGeneration property to on.

• In the custom module, set the Addition, Multiplication,TanhLayer, and Sigmoid properties to on. If the LSTM layer, state activation function is set to relu, set the TanhLayer property to off.

This code output shows you the deep learning processor configuration for a shipping recurrent layer bitstream.

hPC = dlhdl.ProcessorConfig(Bitstream = "zcu102_lstm_single")

hPC = 

                    Processing Module "conv"
                            ModuleGeneration: 'off'

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                         GELUBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                     Sigmoid: 'on'
                                  SwishLayer: 'off'
                                   TanhLayer: 'on'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'
                            UseVendorLibrary: 'on'
                     LayerNormalizationBlock: 'off'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 250
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''