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Multiple Frame Support

Deep Learning HDL Toolbox™ supports multiple frame mode that enables you to write multiple images into the Double Data Rate (DDR) memory and read back multiple results at the same time. To improve the performance of your deployed deep learning networks, use multiple frame mode.

Input DDR Format

Formatting the input images to meet the multiple frame input DDR format requires:

  • The start address of the input data for the DDR

  • The DDR offset for a single input image frame

This information is automatically generated by the compile method. For more information on the generated DDR address offsets, see Use Compiler Output for System Integration.

You can also specify the maximum number of input frames as an optional argument in the compile method. For more information, see Generate DDR Memory Offsets Based On Number of Input Frames.

Output DDR Format

Retrieving the results for multiple image inputs from the output area of the DDR requires:

  • The start address of the output area of the DDR

  • The DDR offset of a single result

The output results have to be formatted to be a multiple of the FC output feature size. The information and formatting are automatically generated by the compile method. For more information on the generated DDR address offsets, see Use Compiler Output for System Integration.

Manually Enable Multiple Frame Mode

After the deep learning network has been deployed, you can manually enable the multiple frame mode by writing the number of frames through a network configuration (NC) port. To manually enter the multiple frame mode at the MATLAB® command line enter:

dnnfpga.hwutils.writeSignal(1, dnnfpga.hwutils.numTo8Hex(addrMap('nc_op_image_count')),15,hT);

The function addrMap('nc_op_image_count') returns the AXI register address for nc_op_image_count, 15 is the number of images and hT represents the dlhdl.Target class that contains the board definition and board interface definition. For more information about the AXI register addresses, see Deep Learning Processor Register Map.

See Also

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