Get Started with HDL Coder
HDL Coder™ enables high-level design for FPGAs, SoCs, and ASICs by generating portable, synthesizable Verilog®, SystemVerilog, and VHDL® code from MATLAB® functions, Simulink® models, and Stateflow® charts. You can use the generated HDL code for FPGA programming, ASIC prototyping, and production design.
HDL Coder includes a workflow advisor that automates prototyping generated code on Xilinx®, Intel®, and Microchip boards and generates IP cores for ASIC and FPGA workflows. You can optimize for speed and area, highlight critical paths, and generate resource utilization estimates before synthesis. HDL Coder provides traceability between Simulink models and the generated Verilog, SystemVerilog, and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
- Create HDL-Compatible Simulink Model
Create a model and check compatibility for HDL code generation.
- Generate HDL Code from Simulink Model
Generate VHDL, Verilog and SystemVerilog code from Simulink models.
- Verify Generated HDL Code from Simulink Model
Generate an HDL test bench to verify the VHDL or Verilog Code.
- HDL Code Generation and FPGA Synthesis from Simulink Model
Generate code and synthesize your Simulink design on the target FPGA.
About HDL Code Generation
- Basic HDL Code Generation Workflow
Follow the workflow for HDL code generation and FPGA synthesis from MATLAB and Simulink algorithms.
- Generation of Clock Bundle Signals in HDL Coder
How HDL Coder generates clock, reset, and clock enable signals in the HDL code.
HDL Coder Overview
Generate VHDL and Verilog code for FPGA and ASIC designs using HDL Coder
Using Simulink to Deploy a MATLAB Algorithm on an FPGA or ASIC
Learn how to take a MATLAB DSP algorithm through Simulink, Fixed-Point Designer™, and HDL Coder, and target an FPGA or ASIC