AXI4 Write
R2026bWrite data to IP core on the target hardware through AXI4-Lite interface
Libraries:
HDL Coder Support Package for Intel FPGA and SoC Devices
Description
Add-On Required: This feature requires the HDL Coder Support Package for Intel FPGA and SoC Devices add-on.
Use the AXI4 interface to write vector data from the embedded processor to a contiguous group of registers on the Programmable Logic IP Core. The AXI4 Write block supports only the AXI4-Lite protocol, allowing for simple, low-throughput memory-mapped communication. Typical uses for this protocol include writing to control and status registers.
The sample rate of the block input signal controls how often this block writes data to the register.
Examples
Ports
Input
Parameters
Version History
Introduced in R2014b
