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Clock edge

Active clock edge

Model Configuration Pane: Global Settings

Description

Specify the active clock edge that triggers Verilog® or SystemVerilog always blocks or VHDL® process blocks in the generated HDL code.

Settings

Rising (default) | Falling

Default: Rising.

Rising

The rising edge, or 0-to-1 transition, is the active clock edge.

Falling

The falling edge, or 1-to-0 transition, is the active clock edge.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','ClockEdge','Falling')
makehdl('sfir_fixed/symmetric_fir')

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir','ClockEdge','Falling')

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: ClockEdge
Type: character vector
Value: 'Rising' | 'Falling'
Default: 'Rising'

Version History

Introduced in R2014a

See Also

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