Specify Altera Qsys project file
the Qsys project file that contains the Altera® Qsys embedded
system design. Use this method if your synthesis tool is Altera Quartus
qsys_project_file— Qsys project file
Qsys project file for Altera Qsys embedded system design, specified as a character vector.
If you have more than one AXI Master IP, in the custom qsys project file, you must make sure that the AXI Master IPs connect to the same AXI Interconnect IP. The AXI4 slave interfaces in the HDL IP core also connect to this Interconnect.
If your synthesis tool is Xilinx® Vivado®,
If your synthesis tool is Xilinx ISE, use the