Check architecture name
Check ID:
com.mathworks.HDL.ModelChecker.runArchitectureNameChecks
Check ID:
com.mathworks.HDL.ModelAdvisor.runArchitectureNameChecks
Check VHDL architecture name in the generated HDL code.
Description
This check verifies whether the architecture name is rtl when
you generate code with VHDL as the target language. This check corresponds to rule
1.A.F.1 of the industry-standard rules.
Available with Simulink®, HDL Coder™, Fixed-Point Designer™, and MATLAB® Coder™.
Results and Recommended Actions
To fix this warning, click Modify Settings and the code
generator updates the VHDLArchitectureName setting to
rtl to adhere to the industry-standard rule.
Capabilities and Limitations
Runs on library models.
Analyzes content in all masked subsystems.
Analyzes only the functions that the Simulink model directly references.
See Also
Rule 1.A.F.1 of Basic Coding Practices.
