The HDL Workflow Advisor guides you through the stages of generating HDL code for a Simulink® subsystem and the FPGA design process, such as:
Checking the model for HDL code generation compatibility and automatically fixing incompatible settings.
Generation of HDL code, a test bench, and scripts to build and run the code and test bench.
Generation of cosimulation or SystemVerilog DPI test benches and code coverage (requires HDL Verifier™).
Synthesis and timing analysis through integration with third-party synthesis tools.
Back-annotation of the model with critical path information and other information obtained during synthesis.
Complete automated workflows for selected FPGA development target devices, including FPGA-in-the-loop simulation (requires HDL Verifier), and the Simulink Real-Time™ FPGA I/O workflow.
To select test bench and code coverage options for generating HDL code from a Simulink model using the HDL Workflow Advisor:
Perform the setup steps in HDL Code Generation and FPGA Synthesis from Simulink Model.
In Step 3.1.4 of the HDL Workflow Advisor, Set Testbench Options, select test bench and code coverage options from the Test Bench Generation Output section. The coder generates a build-and-run script for your test bench and the Simulation tool you specify. If you select multiple test bench options, the coder generates one test bench and script for each type of test bench selected. If you select HDL code coverage, the test bench scripts turn on code coverage for your generated HDL code. For more information about the different kinds of test benches, see Choose a Test Bench for Generated HDL Code. After you select your test bench options, click Apply.
In Step 3.2, Generate RTL Code and Testbench, select Generate test bench. Click Apply, and then click Run This Task. The coder generates HDL code for your subsystem, and the test benches and scripts you selected in step 3.1.3.
If you selected Cosimulation model, then step 3.3, Verify with HDL Cosimulation, appears in the HDL Workflow Advisor. This step automatically runs the generated cosimulation model. The model compares the result of the HDL code running in your HDL simulator with the output of your Simulink subsystem.
If you selected HDL test bench, the coder generates a compile
subsystemname_tb_compile, and a run
. The script
file extension depends on your selected simulator. For example, at the command line in
the Mentor Graphics®
ModelSim® simulator, change to the
hdl_prj/hdlsrc/ folder and
do symmetric_fir_compile.do do symmetric_fir_tb_compile.do do symmetric_fir_tb_sim.do
If you selected SystemVerilog DPI test bench, the coder
generates a script file,
, that compiles
the HDL code and runs the test bench simulation. The script file extension depends on
your selected simulator. For example, at the command line in the Mentor Graphics
ModelSim simulator, change to the
hdl_prj/hdlsrc/ folder and
run this command:
If you selected HDL code coverage, the code coverage report
from running any test bench, including the
cosimulation model, is saved in